To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels each have a diode. The luminance of the EL elements of each in the display pixels is controlled in accordance with the amount of electric current flowing in each of the diodes.

Semiconductor display device

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

To improve color reproduction areas in a display device having light-emitting elements. A display region has a plurality of picture elements. Each picture element includes: first and second pixels each including a light-emitting element which has a chromaticity whose x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more; third and fourth pixels each including a light-emitting element which has a chromaticity whose y-coordinate in the diagram is 0.55 or more; and fifth and sixth pixels each including a light-emitting element which has a chromaticity whose x-coordinate and y-coordinate in the diagram are 0.20 or less and 0.25 or less, respectively. The light-emitting elements in the first and second pixels have different emission spectrums from each other; the light-emitting elements in the third and fourth pixels have different emission spectrums from each other; and the light-emitting elements in the fifth and sixth pixels have different emission spectrums from each other.

Display device and electronic device

Advances in IC fabrication technology, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, local area networks, memory buses, and multiprocessor interconnection networks. Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of highspeed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block.

High-speed electrical signaling: overview and limitations

The application of adaptive power-supply regulation is extended to serial links The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution A prototype chip fabricated in 025-/spl mu/m CMOS process operates at 065-50 Gb/s while dissipating 97-380 mW

Adaptive supply serial links with sub-1-V operation and per-pin clock recovery

A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >

An experimental high-density DRAM cell with a built-in gain stage

A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

Cable with circuitry for asserting stored cable data or other information to an external device or user

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 /spl mu/m CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns. >

A CMOS serial link for fully duplexed data communication

A low-jitter 5000ppm spread-spectrum clock generator is implemented in a 0.18/spl mu/m CMOS process. By using 10 multi-phase clocks and a /spl Delta//spl Sigma/ modulator with periodic input, the chip has a deterministic jitter of 25ps due to spread-spectrum clocking and an amount of spreading of 5000ppm.

A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3/spl times/-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of the data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the linearized model of the phase detector, the loop dynamics of the CDR are analyzed. Integrated in a single-chip transceiver with 0.25-/spl mu/m CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10/sup -13/ when the magnitude of data jitter reaches 60.5% of bit time.

Gijung Ahn

Papers

An experimental high-density DRAM cell with a built-in gain stage

Cable with circuitry for asserting stored cable data or other information to an external device or user

A CMOS serial link for fully duplexed data communication

A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit