Showing papers in "IEEE Journal of Solid-state Circuits in 1995"
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Abstract: 1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >
1,338 citations
TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Abstract: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >
623 citations
TL;DR: In this paper, an analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented, which achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz without requiring any external component or any tuning or trimming.
Abstract: An analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products.
489 citations
TL;DR: In this article, the authors describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic.
Abstract: With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 /spl mu/m CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry. >
282 citations
TL;DR: In this article, the implementation of two high-frequency building blocks for low-phase-noise 1.8 GHz PLL in a standard 0.7/spl mu/m CMOS process is discussed.
Abstract: The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-/spl mu/m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW.
255 citations
TL;DR: This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology.
Abstract: Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW. >
199 citations
TL;DR: In this article, closed-form expressions for the transfer characteristic of a low-power monolithic RF peak detector were derived and compared with computer simulation and experimental measurements, and the results showed that the transfer characteristics of a monolithic peak detector are similar to those of a single-input single-output (SISO) antenna.
Abstract: Closed-form expressions are derived for the transfer characteristic of a low-power monolithic RF peak detector. These are compared with computer simulation and experimental measurements. >
192 citations
TL;DR: This paper presents the first VLSI single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points, and could therefore be introduced in the coming years in digital terrestrial TV receivers at low cost.
Abstract: Large-scale single-frequency networks are now being considered in Europe as very promising network topologies to achieve drastic savings in spectrum usage for digital terrestrial television transmission. Such networks are possible using the COFDM system, with large guard intervals (more than 200 /spl mu/s) to absorb long echoes. In order to limit the spectral efficiency loss to about 20%, very long size fast Fourier transforms (up to 8 K complex points) have to be performed in real time for the demodulation of every COFDM symbol (every 1 ms). This paper presents the first VLSI single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points. Due to its pipelined architecture, it can perform an 8 K FFT every 400 /spl mu/s and a 1 K FFT every 50 /spl mu/s. All the storage is onchip, so that no external memories are required. A new internal result scaling technique, called convergent block floating point, has been introduced in order to minimize the required storage for a given quantization noise, The chip, 1 cm/sup 2/ large with 1.5 million transistors, has been designed in a 3.3 V-0.5 /spl mu/m triple-level metal CMOS process and is fully functional. The 8 K complex FFT function could therefore be introduced in the coming years in digital terrestrial TV receivers at low cost. >
187 citations
TL;DR: A novel CMOS integrated circuit for a batteryless transponder system that gives a superior performance in reading distance due to separation of the powering and data transmission phases-compared to systems with continuous powering and damping modulation.
Abstract: A novel CMOS integrated circuit for a batteryless transponder system is presented. Batteryless transponders require contactless transmission of both the information and power between a mobile data carrier and a stationary or handheld reader unit. The operating principle of this system gives a superior performance in reading distance due to separation of the powering and data transmission phases-compared to systems with continuous powering and damping modulation. This paper describes the function of the transponder IC and the circuit design techniques used for the various building blocks. >
183 citations
TL;DR: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.
Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
179 citations
TL;DR: In this paper, a CMOS mixer topology for use in highly integrated downconversion receivers is presented, which is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch.
Abstract: A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 /spl mu/m CMOS process. It takes up 1 mm/sup 2/ of total chip area and its power consumption is 1.3 mW from a single 5 V power supply. >
TL;DR: A general theoretic framework for the solution of the state assignment problem is formulated, and different algorithms trading off computational effort for quality are proposed, resulting in a 16% average reduction in switching activity.
Abstract: We address the problem of reducing the power dissipated by synchronous sequential circuits. We target the reduction of the average switching activity of the input and output state variables by minimizing the number of bit changes during state transitions. Using a probabilistic description of the finite state machines, we propose a state assignment algorithm that minimizes the Boolean distance between the codes of the states with high transition probability. We formulate a general theoretic framework for the solution of the state assignment problem, and propose different algorithms trading off computational effort for quality. We then generalize our model to take into account the estimated area of a multilevel implementation during state assignment, in order to obtain final circuits where the total power dissipation is minimized. A heuristic algorithm has been implemented and applied to standard benchmarks, resulting in a 16% average reduction in switching activity. >
TL;DR: In this article, a second-order delta-sigma (SDS)/spl Delta/spl Sigma/ modulator was fabricated in a AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates.
Abstract: This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from /spl plusmn/5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first /spl Delta//spl Sigma/ modulator in III-V technology with ideal performance and provides the foundation for extending the use of /spl Delta//spl Sigma/ modulator analog-to-digital converters (ADC's) to radio frequencies (RF). >
TL;DR: In this article, a folding and interpolating technique was used to increase the analog bandwidth of the A/D converter by using a transresistance amplifier at the outputs of the folding amplifiers and the comparators need no offset compensation.
Abstract: A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm/sup 2/ in 0.8 /spl mu/m CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.
TL;DR: In this article, a 1.9 GHz wireless receiver front-end (low-noise preamplifier and mixer) is described that incorporates monolithic microstrip transformers for significant improvements in performance compared to silicon broadband designs.
Abstract: A 1.9 GHz wireless receiver front-end (low-noise preamplifier and mixer) is described that incorporates monolithic microstrip transformers for significant improvements in performance compared to silicon broadband designs. Reactive feedback and coupling elements are used in place of resistors to lower the front-end noise figure through the reduction of resistor thermal noise, and this also allows both circuits to operate at supply voltages below 2 V. These circuits have been fabricated in a production 0.8 /spl mu/m BiCMOS process that has a peak npn transistor transit frequency (f/sub T/) of 11 GHz. At a supply voltage of 1.9 V, the measured mixer input third-order intercept point is +2.3 dBm with a 10.9 dB single-sideband noise figure. Power dissipated by the mixer is less than 5 mW. The low-noise amplifier input intercept is -3 dBm with a 2.8 dB noise figure and 9.5 dB gain. Power dissipation of the preamplifier is less than 4 mW, again from a 1.9 V supply.
TL;DR: Experimental results of a communication architecture tailored for analog VLSI perceptive systems satisfactorily support the theoretical basis upon which the system was constructed and Extensions to the communication architecture are finally presented.
Abstract: A communication architecture tailored for analog VLSI perceptive systems is proposed. Information is generated on a transmitter array of cells each driving a pulse generator. The resulting pulse-frequency modulated signals are transmitted through the nonarbitered, asynchronous access of pulses to a common bus. Pulses are decoded and accumulated in a receiver chip and the mapping of the activity distribution of the transmitter onto the receiver is achieved. One possible implementation of these principles is presented. The circuit description of all blocks is given and experimental results are shown: they satisfactorily support the theoretical basis upon which the system was constructed. Extensions to the communication architecture are finally presented. >
TL;DR: In this article, the authors present a new approach toward performance-driven placement of analog integrated circuits, where the freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications.
Abstract: This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples. >
TL;DR: Two second-order bandpass delta-sigma A/D modulators have been implemented in a 0.8 /spl mu/ BiCMOS process to demonstrate the feasibility of converting a 10.7 MHz radio IF signal to digital form.
Abstract: Two second-order bandpass delta-sigma A/D modulators have been implemented in a 0.8 /spl mu/ BiCMOS process to demonstrate the feasibility of converting a 10.7 MHz radio IF signal to digital form. The circuits, based on switched-capacitor biquads, demonstrated 57 dB SNR in a 200 kHz bandwidth when clocked at 42.8 MHz, dissipating 60 mW from a 5 V supply. The two modulators use different clocking strategies to allow evaluation of a tradeoff between active and passive sensitivities. >
TL;DR: The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals and a comparison of results is presented.
Abstract: The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals. The design has been processed in 0.8- and 0.6-/spl mu/m CMOS processes. A comparison of results is presented. >
TL;DR: In this paper, a fully integrated Class E power amplifier module operating at 835 MHz is designed, fabricated, and tested, implemented in a self-aligned-gate, depletion mode 0.8-/spl mu/m GaAs MESFET process.
Abstract: A Class E power amplifier for mobile communications is presented. The advantages of Class E over Class B, Class C, and Class F power amplifiers in a low voltage design are discussed. A fully integrated Class E power amplifier module operating at 835 MHz is designed, fabricated, and tested. The circuit is implemented in a self-aligned-gate, depletion mode 0.8-/spl mu/m GaAs MESFET process. The amplifier delivers 24 dBm of power to the 50-/spl Omega/ load with a power added efficiency greater than 50% at a supply voltage of 2.5 V. The power dissipated in the integrated matching networks is 1.5 times the power dissipated in the transistor. >
TL;DR: In this paper, a time-to-digital converter (TDC) with 780 ps lsb and 10-spl mu/s input range has been integrated in a 1.2-/spl µ/m CMOS technology.
Abstract: A time-to-digital converter, TDC, with 780 ps lsb and 10-/spl mu/s input range has been integrated in a 1.2-/spl mu/m CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5/spl plusmn/0.5 V, and the operating temperature range is -40 to +60/spl deg/C. Single-shot accuracy is 3 ns and accuracy after averaging is /spl plusmn/120 ps with input time intervals 5-500 ns. In the total input range of 10 /spl mu/s, the final accuracy after averaging is /spl plusmn/200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm/spl times/2.5 mm. >
TL;DR: In this paper, a bandgap voltage reference circuit with a 3 V power supply and compatible with a digital CMOS process is described. But the use of a simple circuit topology results in a small silicon area of 0.07 mm/sup 2/, a power consumption of 1 mW and a high power supply rejection over a wide frequency band.
Abstract: This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm/sup 2/, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm//spl deg/C and a standard deviation of 20 mV without trimming. >
TL;DR: In this article, a novel circuit technology with Surrounding gate transistors (SGT's) for ultra high density DRAM's is described, where an SGT is employed to all the transistors within a chip.
Abstract: This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >
TL;DR: A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented in this article with a spectral purity of -84.3 dBc and frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles.
Abstract: A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 /spl mu/m triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6/spl times/6.1 mm/sup 2/. Power dissipation is 2 W at 200 MHz and 5 V. >
TL;DR: In this article, a second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 /spl mu/m CMOS technology.
Abstract: A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 /spl mu/m CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm/sup 2/ and it dissipates 67.5 mW of power from a 5 V supply. >
TL;DR: In this article, the authors describe a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication, which is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end.
Abstract: This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 /spl mu/m CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns. >
TL;DR: In this article, the implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed, where the control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4.
Abstract: A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4/spl times/4 CNN prototype system has been designed in a 2.4 /spl mu/m CMOS technology and successfully tested. The cell density is 380 cells/cm/sup 2/ and the cell time constant is 10 /spl mu/s. The current drain for a typical template is 40 /spl mu/A/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128/spl times/128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies. >
TL;DR: In this article, a 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 /spl mu/m CMOS technology is described.
Abstract: A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 /spl mu/m CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 /spl mu/s, PLL power dissipation below 10 mW as well as phase error and jitter below /spl plusmn/100 ps have been measured. The total area of the PLL is 0.52 mm/sup 2/. >
TL;DR: In this paper, a single-ended input but internally differential 10 b, 20 µample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply.
Abstract: A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 /spl mu/m CMOS technology exhibits a DNL of /spl plusmn/0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm/sup 2/. >
TL;DR: In this article, the authors present and compare five approaches for modeling the energy consumption of CMOS circuits and apply them to SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities.
Abstract: The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV/sup 2/ prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within /spl plusmn/1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings. >