Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

Surface Chemistry of Ruthenium Dioxide in Heterogeneous Catalysis and Electrocatalysis: From Fundamental to Applied Research

Atomic layer deposition (ALD) has been studied for several decades now, but the interest in ALD of metal and nitride thin films has increased only recently, driven by the need for highly conformal nanoscale thin films in modern semiconductor device manufacturing technology. ALD is a very promising deposition technique with the ability to produce thin films with excellent conformality and compositional control with atomic scale dimensions. However, the applications of metals and nitrides ALD in semiconductor device processes require a deeper understanding about the underlying deposition process as well as the physical and electrical properties of the deposited films. This article reviews the current research efforts in ALD for metal and nitride films as well as their applications in modern semiconductor device fabrication.

Atomic layer deposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing

The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO2 or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate dielectric of a MOS transistor and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for gate dielectrics like SiO2, Al2O3, Si3N4, ZrO2, and HfO2 were extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate work functions on the gate dielectric material. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future MOS technology incorporating high-κ gate dielectrics.

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Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

Metal–oxide–semiconductor capacitors were used to study the interaction of Hf and Zr gate electrodes on SiO2, ZrSixOy, and ZrO2. A large reduction in the SiO2 equivalent oxide thickness accompanied by an increase in the leakage current was observed with Hf and Zr electrodes when subjected to anneal temperatures as low as 400 °C. The reduction in electrical thickness as observed from the capacitance–voltage measurements was attributed to the combination of (a) physical thinning of the SiO2 and (b) formation of a high-K layer. A severe instability of Zr and Hf electrodes was also observed on ZrSixOy and ZrO2 dielectrics. This behavior of Zr and Hf gates was attributed to high negative enthalpy of oxide formation and high oxygen solubility resulting in the reduction of the gate dielectric and subsequent oxygen diffusion to the gate electrode.

Use of metal–oxide–semiconductor capacitors to detect interactions of Hf and Zr gate electrodes with SiO2 and ZrO2

The rutile stoichiometric phase of RuO2, deposited via reactive sputtering, was evaluated as a gate electrode on chemical vapor deposited ZrO2 and Zr silicate for Si–p-type metal–oxide–semiconductor (PMOS) devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures of 400, 600, and 800 °C in N2. X-ray diffraction was measured to study grain structure and interface reactions. The resistivity of RuO2 films was 65.0 μΩ cm after 800 °C annealing. Electrical properties were evaluated on MOS capacitors, which indicated that the work function of RuO2 was ∼5.1 eV, compatible with PMOS devices. Post-RuO2 gate annealing up to 800 °C, resulted in only a 1.4 A equivalent oxide thickness (Tox-eq) change and 0.2 V flatband voltage change for Zr silicate and a 4 A Tox-eq change for ZrO2 dielectrics. Tantalum electrodes were also studied on ZrO2 as a comparison of the stability of RuO2 electrodes.

Characterization of RuO2 electrodes on Zr silicate and ZrO2 dielectrics

This paper describes the characteristics of binary metallic alloys of Ta and Ru for gate electrode applications. The work function of this alloy can be varied from 4.2 eV to 5.2 eV by controlling the composition thereby enabling its use in both NMOS and PMOS devices. Excellent thermal stability up to 1000/spl deg/C was observed in alloy compositions suitable for both NMOS and PMOS devices. It is believed that the Ru/sub 1/Ta/sub 1/ phase of the film and formation of Ru-Ta bonds improves the thermal stability of the gate-dielectric interface while maintaining appropriate work functions.

Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices

In this work, we have studied the electrical and thermal stability of Ru and RuO2 electrodes on ZrO2 and Zr-silicate dielectrics. Very low resistivity Ru and rutile stoichiometric RuO2 films, deposited by reactive sputtering, were evaluated as gate electrodes on ultrathin ZrO2 and Zr-silicate (∼2.7 nm) films for Si-PMOS devices. Thermal and chemical stability of the electrodes were studied at annealing temperatures up to 800°C in N2 followed by a forming gas anneal. X-ray diffraction (XRD), transmission electron microscopy (TEM), and x-ray photoelectron spectroscopy (XPS) methods were used to study grain structure and interface reactions. Electrical properties were evaluated using MOS capacitors. The role of oxygen in these dielectrics was studied by comparing equivalent oxide thickness (EOT) changes as a function of annealing temperature for capacitors with ZrO2 and Zr-silicate dielectrics. For capacitors with Ru and RuO2 gate electrodes on both ZrO2 and Zr-silicate, excellent stability of EOT was detected. Flatband voltage and gate current as a function of annealing temperature were also studied. These studies indicate that Ru and RuO2 are promising gate electrodes for P-MOSFETs.

Electrical properties of Ru and RuO2 gate electrodes for Si-PMOSFET with ZrO2 and Zr-silicate dielectrics

This paper describes a metal gate process, which provides tunable work function values and ease of integration for dual metal gate process flow Vertical stacks of Ru and Ta layers were subjected to high temperature anneals to promote intermixing which resulted in /spl phi//sub m/ tuning It was found that Ru/Ta stacks provided up to 04 eV reduction in /spl phi//sub m/ compared to Ru To increase this change, stacks of Ru/sub 50/Ta/sub 50//Ru were also evaluated and nearly a 08 eV change in /spl phi//sub m/ was observed between Ru/sub 50/Ta/sub 50//Ru and Ru/sub 50/Ta/sub 50/ electrodes

Greg Heuss

Papers

Use of metal–oxide–semiconductor capacitors to detect interactions of Hf and Zr gate electrodes with SiO2 and ZrO2

Characterization of RuO2 electrodes on Zr silicate and ZrO2 dielectrics

Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices

Electrical properties of Ru and RuO2 gate electrodes for Si-PMOSFET with ZrO2 and Zr-silicate dielectrics

Tunable work function dual metal gate technology for bulk and non-bulk CMOS