In this brief, a low-cost very large scale integration (VLSI) architecture is designed for multistandard inverse transform. The proposed architecture is used in multistandard decoder of MPEG-2, MPEG-4 ASP, H.264/AVC and VC-1. Two circuit share strategies, factor share (FS) and adder share (AS), are applied to the inverse transform architecture for saving its circuit resource. It is shown that the proposed multistandard inverse transform architecture can support the real-time decoding of 1920 × 1080@60 Hz high-definition video at the cost of low circuit resource.

A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform

The fast Fourier transform (FFT) algorithm was developed by Cooley and Tukey in 1965. It could reduce the computational complexity of discrete Fourier transform significantly from $$O(N^2)$$
 to $$O(N\log _2 {N})$$
 . The invention of FFT is considered as a landmark development in the field of digital signal processing (DSP), since it could expedite the DSP algorithms significantly such that real-time digital signal processing could be possible. During the past 50 years, many researchers have contributed to the advancements in the FFT algorithm to make it faster and more efficient in order to match with the requirements of various applications. In this article, we present a brief overview of the key developments in FFT algorithms along with some popular applications in speech and image processing, signal analysis, and communication systems.

50 Years of FFT Algorithms and Applications

This brief presents a reconfigurable VLSI architecture which is designed for multi-transform codec in several video coding standards of MPEG-2/4, VC-1, H.264/AVC and AVS. The reconfigurable multiple constant multiplication algorithm with two fusing strategies is provided to generate constant multipliers in the matrix calculation blocks. Additionally, adder-sharing strategy is adopted in the unified preprocessing/postprocessing block to save circuit areas. The proposed architecture can support different standards through static reconfiguration and forward/inverse transform functions through dynamic reconfiguration. It is suitable for the real-time processing of 1080P HD video codec with six video standards transforms.

A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design

This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.

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The Serial Commutator FFT

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultrawideband systems. The proposed 128-point FFT processor employs both a modified radix-2 4 algorithm and a radix-2 3 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems

In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2times2, 4times4, and 8times8 inverse transforms of H.264/AVC and the 1-D 8times8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by adding the offset computations, and it is implemented with the pipelined architecture. Thus, the hardware cost of the proposed sharing architecture is smaller than that of the individual and separate designs. With regular modularity, the proposed sharing architecture is suitable to achieve H.264/AVC and AVS signal processing by VLSI implementations.

Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications

In this letter, the fast one-dimensional (1-D) algorithms and their sharing design for 1-D inverse integer transforms of H.264/AVC and VC-1 are proposed by using the matrix decompositions with the sparse matrices and the matrix offset computations. The computational complexities of the proposed fast 1-D 4 times 4 and 8 times 8 inverse integer transforms for H.264/AVC are the same as those of the previous fast methods. Then the shift operations of the proposed fast 1-D inverse integer transform for VC-1 are equivalent to those of the previous fast method. For playback environments, the video decoder can support the multiple modes, which include H.264/AVC and VC-1 video standards. The proposed hardware sharing architecture requires lower hardware cost than the individual and separate design for the VLSI realization.

Efficient Low-Cost Sharing Design of Fast 1-D Inverse Integer Transform Algorithms for H.264/AVC and VC-1

In this brief, the fast 1D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1D integer transforms are hardware shared, and they can be applied to the 2D transform scheme. The hardware costs of the proposed fast 1D and 2D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec.

Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1

In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple. The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations. The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UIMC 0.18?m standard cell technology. The throughput rate of this implementation is suitable for WiMLAX 802.16a application, whose maximum sample rate is 32MHz.

Guo-An Su

Papers

Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications

Efficient Low-Cost Sharing Design of Fast 1-D Inverse Integer Transform Algorithms for H.264/AVC and VC-1

Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1

A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture

Pruning fast Fourier transform algorithm design using group-based method