Proceedings ArticleDOI
A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture
Chih-Peng Fan,Mau-Shih Lee,Guo-An Su +2 more
- pp 1935-1938
TLDR
A low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems, based on the radix-16 FFT algorithm, which needs less complexity than both complexities of the previous FFT structures in 256- point FFT applications.Abstract:
In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple. The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations. The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UIMC 0.18?m standard cell technology. The throughput rate of this implementation is suitable for WiMLAX 802.16a application, whose maximum sample rate is 32MHz.read more
Citations
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Journal ArticleDOI
50 Years of FFT Algorithms and Applications
TL;DR: A brief overview of the key developments in FFT algorithms along with some popular applications in speech and image processing, signal analysis, and communication systems are presented.
Journal ArticleDOI
The Serial Commutator FFT
TL;DR: This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT, based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated.
Journal ArticleDOI
A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems
Sang-In Cho,Kyu-Min Kang +1 more
TL;DR: The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐ point FFT architectures.
Journal ArticleDOI
A New Representation of FFT Algorithms Using Triangular Matrices
TL;DR: The triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.
Journal ArticleDOI
A Survey on Pipelined FFT Hardware Architectures
TL;DR: A survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes and divides the architectures into serial and parallel.
References
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Book
Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
Proceedings ArticleDOI
A new approach to pipeline FFT processor
Shousheng He,M. Torkelson +1 more
TL;DR: A new VLSI architecture for a real-time pipeline FFT processor is proposed, derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach, which has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the Radix-2 algorithm.
Journal ArticleDOI
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
TL;DR: VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints.
Proceedings ArticleDOI
Designing pipeline FFT processor for OFDM (de)modulation
Shousheng He,M. Torkelson +1 more
TL;DR: By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized and the area/power efficiency has been enhanced.
Journal ArticleDOI
Fourier Transform Computers Using CORDIC Iterations
TL;DR: The CORDIC iteration is applied to several Fourier transform algorithms and a new, especially attractive FFT computer architecture is presented as an example of the utility of this technique.