We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed.

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range

A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves phase noise and spurious tone performance comparable to those of a high-performance analog PLL. It is enabled by a new second-order frequency-to-digital converter that uses a dual-mode ring oscillator and digital logic instead of a charge pump and ADC. It also incorporates a new technique to reduce excess phase noise that would otherwise be caused by component mismatches when the DCO input is near integer boundaries. The PLL's largest in-band fractional spur is -60 dBc, its worst-case reference spur is -81 dBc, and its phase noise is -93, -126, and -151 dBc/Hz at offsets of 100 kHz, 1 MHz, and 20 MHz, respectively. Its active area is 0.34 mm 2 and it dissipates 15.6 mW from a 1 V supply.

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the $N_{b}$ -bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of $N_{b}=2$ seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper.

Jitter Minimization in Digital PLLs with Mid-Rise TDCs

A CMOS phase noise filter (PNF) enabled by the passive delay line (DL) and phase detector/charge pump (PD/CP)-based frequency discriminator is proposed. The delay-locked loop and dc offset cancellation loop are embedded in the PNF to achieve fully automatic calibration. The PNF is insensitive to the amplitude noise due to the PD/CP phase extraction feature. With a 20-ns DL, the PNF achieves 10.6/15-dB phase noise suppression with −116.6/−114.9-dBc/Hz phase noise sensitivity at 1-MHz offset in low/high-gain mode, respectively. The suppression offset frequency range is 100 kHz–12 MHz with 9.97–10.087-GHz input frequency range. The phase noise sensitivity improves to −119.9/−123.4 dBc/Hz at 1-MHz offset with the 40/80-ns DL, respectively. The integrated jitter from 10 kHz to 100 MHz is 176/111/85.5 fs with the 20/40/80-ns DL. The PNF is fabricated in a 65-nm CMOS process with the chip area of 1.68 mm $\times 1.5$ mm and power consumption of 102 mW. The PNF provides a new approach to further enhance the phase noise and jitter performance especially at low offset frequencies.

A CMOS Phase Noise Filter With Passive Delay Line and PD/CP-Based Frequency Discriminator

Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and low supply voltages, which makes them better-suited to highly-scaled CMOS technology [1-6]. However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is because all fractional-N PLLs introduce quantization noise, and in prior digital PLLs this noise has higher power or spurious tones than in comparable analog PLLs. Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumps and ADCs that have so far limited their performance and minimum supply voltages [7,8]. This paper presents an FDC-PLL that avoids these limitations by implementing the functionality of a charge pump and ADC with a simple dual-mode ring oscillator (DMRO) and digital logic. Also demonstrated is a new quantization noise cancellation (QNC) technique that relaxes the fundamental bandwidth versus quantization noise tradeoff inherent to most fractional-TV PLLs. The new techniques enable state-of-the-art spurious tone performance and very low phase noise with a lower power dissipation and supply voltage than previously published state-of-the-art PLLs in the same class shown in Fig. 25.1.6.

Guobi Zhao

Papers

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation