Ferrofluids for heat transfer enhancement under an external magnetic field

A data center cooling system includes a thermosiphon, an actuator coupled to the thermosiphon, and a controller. The thermosiphon includes an evaporator; a condenser; and at least one conduit coupled between the evaporator and the condenser to transport a working fluid between the evaporator and the condenser. The controller is coupled to the actuator and configured to operate the actuator to adjust a liquid level of the working fluid in the evaporator based, at least in part, on a parameter associated with a heat load of one or more data center heat generating computing devices.

Cooling electronic devices in a data center

Using microfluidic cooling to achieve thermal management of three-dimensional integrated circuits (ICs) is recognized as a promising method of extending Moore law progression in electronic components and systems. Since the U.S. Defense Advanced Research Projects Agency launched Intra/Inter Chip Enhanced Cooling thermal packaging program, the method of using microfluidic cooling in 3D ICs has been under continuous development. This paper presents an analysis of all publications available about the microfluidic cooling technologies used in 3D IC thermal management, and summarized these research works into six categories: cooling structure design, co-design issues, through silicon via (TSV) influence, specific chip applications, thermal models, and non-uniform heating and hotspots. The details of these research works are given, future works are suggested.

3D Integrated Circuit Cooling with Microfluidics.

Single-phase thermal and hydraulic performance of embedded silicon micro-pin fin heat sinks using R245fa

Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).

Selector for low voltage embedded memory

In modern integrated systems, interconnect and thermal management technologies have become two major limitations to system performance. In this paper, a number of technologies are presented to address these challenges. First, low-loss polymer-embedded vias are demonstrated in thick wafers compatible with microfluidics. Next, fluidic I/Os for delivery of fluid to microfluidic heat sinks are demonstrated in assembled 2.5D and 3D stacks. Then thermal coupling between dice in 2.5D and 3D systems is explored. Lastly, the utility of microfluidic cooling is demonstrated through an FPGA, built in a 28nm process, with a monolithically integrated microfluidic heat sink.

Embedded cooling technologies for densely integrated electronic systems

Microfluidic cooling has been demonstrated as an effective means of cooling microelectronic circuits with a very low convective thermal resistance and potential for integration in close proximity to the area of heat generation. However, microfluidic cooling experiments to date have been limited to silicon with resistive heaters representing the heat generating circuitry. In this paper, a micropin-fin heat sink is etched into the back side of an Altera Stratix V field-programmable gate array (FPGA), built in a 28-nm CMOS process. Thermal and electrical measurements are made running a benchmark pulse compression algorithm on the FPGA. Deionized water is used as a coolant with flow rates ranging from 0.15 to 3.0 mL/s and inlet temperature ranging from 21 °C to 50 °C. An average junction-to-inlet thermal resistance of 0.07 °C/W is achieved.

Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second subchannels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.

An integrated circuit package with enhanced cooling structure

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry

The 2.5-D integration is becoming a common method of tightly integrating heterogeneous dice with dense interconnects for efficient, high-bandwidth inter-die communication. While this tight integration improves performance, it also increases the challenge of heat extraction by increasing aggregate package powers and introducing thermal crosstalk between the adjacent dice. In this article, a microfluidic heat sink is used to cool a 2.5-D Stratix 10 GX field-programmable gate array (FPGA) consisting of an FPGA die surrounded by four transceiver dice. The heat sink utilizes a heterogeneous micropin-fin array with micropin-fin densities that are tailored to the local heat fluxes of the underlying dice. Enabled through a 3-D printed enclosure for fluid delivery, the assembled heat sink has a total height of 6.5 mm, including the tubes used for fluid delivery. The heat sink is tested in an open-loop system with deionized water as a coolant, and thermal performance is compared against a high-end air-cooled heat sink. Improvements in die temperatures, computational density, and thermal coupling between the dice are observed. The effect of the FPGA power on the surrounding transceiver die temperatures was reduced by a factor of ${10}\times$ to over ${100}\times$ when compared with the air-cooled heat sink.

Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization

Gutala Ravi Prakash

Papers

Embedded cooling technologies for densely integrated electronic systems

Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

An integrated circuit package with enhanced cooling structure

Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry

Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization