Showing papers in "IEEE Transactions on Components, Packaging and Manufacturing Technology in 2019"
TL;DR: In this article, a 3D coupled electrothermal model was constructed based on the electrical and thermal characterization results of a MOSFET fabricated via homoepitaxy.
Abstract: The ultrawide bandgap (UWBG) (~4.8 eV) and melt-grown substrate availability of $\beta $ -Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers’ attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of ~1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.
82 citations
TL;DR: A global Fourier image reconstruction method to detect and localize small defects in nonperiodical pattern images that is invariant to translation and illumination, and can detect subtle defects as small as 1-pixel wide in a wide variety of non periodical patterns found in the electronic industry.
Abstract: For defect detection in nonperiodical pattern images, such as printed circuit boards or integrated circuit dies found in the electronic industry, template matching could be the only applicable method to tackle the problem. The traditional template matching techniques work in the spatial domain and rely on the local pixel information. They are sensitive to geometric and lighting changes, and random product variations. The currently available Fourier-based methods mainly work for plain and periodical texture surfaces. In this paper, we propose a global Fourier image reconstruction method to detect and localize small defects in nonperiodical pattern images. It is based on the comparison of the whole Fourier spectra between the template and the inspection image. It retains only the frequency components associated with the local spatial anomaly. The inverse Fourier transform is then applied to reconstruct the test image, where the local anomaly will be restored and the common pattern will be removed as a uniform surface. The proposed method is invariant to translation and illumination, and can detect subtle defects as small as 1-pixel wide in a wide variety of nonperiodical patterns found in the electronic industry.
59 citations
TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.
45 citations
TL;DR: In this paper, a new set of basis functions is proposed to capture the impact of non-Gaussian correlated parameters and then an automatic and optimization-based quadrature method is presented to perform projection-based stochastic collocation with a few simulation samples in the correlated parameter space.
Abstract: Stochastic spectral methods have achieved a great success in the uncertainty quantification of many engineering problems, including variation-aware electronic and photonic design automation. State-of-the-art techniques employ generalized polynomial-chaos expansions and assume that all random parameters are independent or Gaussian correlated. This assumption is rarely true in real applications. How to handle non-Gaussian correlated random parameters is a long-standing and fundamental challenge: It is not clear how to choose basis functions and to perform a projection step in a correlated uncertain parameter space. This paper first presents a new set of basis functions to well capture the impact of non-Gaussian correlated parameters and then proposes an automatic and optimization-based quadrature method to perform projection-based stochastic collocation with a few simulation samples in the correlated parameter space. We further provide some theoretical proofs for the complexity and error bound of our proposed method. The numerical experiments on several synthetic, electronic, and photonic integrated circuit examples show the nearly exponential convergence rate of our approach and its significant ( $700 \times $ – $6000 \times $ ) speedup than Monte Carlo. Many other open problems with non-Gaussian correlated uncertainties can be further solved based on this paper.
44 citations
TL;DR: In this article, a three-line coupled structure (TLCS) is employed in the design of the filtering power divider (FPD) to achieve a broad fractional bandwidth and good frequency selectivity.
Abstract: Three-line coupled structure (TLCS) is employed in the design of the filtering power divider (FPD) to achieve a broad fractional bandwidth and good frequency selectivity in this paper. A detailed theoretical analysis of the proposed FPD is presented by using the calculated method of impedance matrix deduction. To validate the design concept, the proposed initial FPD prototype is electromagnetically simulated, whose performance shows good consistency with that of the proposed theoretical calculation. In addition, a simple quasi-lumped impedance transformer is introduced near the input port to further improve the matching status of the FPD. These two above-mentioned FPDs are both designed with center frequencies of 2.42 GHz and 3-dB fractional bandwidths of over 82.6%, the latter one of which is fabricated and tested. Comparisons between the simulated and measured results are presented with good agreement to verify the calculated predictions.
43 citations
TL;DR: In this article, a simple and reliable method to manage the transient overvoltage and oscillation phenomena in a solid-state dc circuit breaker based on the silicon carbide (SiC) metaloxide-semiconductor field effect transistor (MOSFET) is presented.
Abstract: The transient overvoltage and oscillation phenomena, which are caused by its high switching speed in a solid-state dc circuit breaker based on the silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET), are a crucial problem. This paper presents a simple and reliable method to manage such a problem. An equivalent circuit model for SiC MOSFET is primarily established. The influence of stray inductance in energy absorption loop on the turn-off characteristics of the dc circuit breaker is then analyzed. Subsequently, possible typical overvoltage suppression methods, such as using a resistor–capacitor snubber circuit and increasing gate resistance and parallel capacitance between the gate and source, are simulated and analyzed. Thereafter, a peak voltage suppression method that does not sacrifice the fast switching capability of SiC MOSFET is proposed based on different amounts of energy absorbed by metal oxide varistors (MOVs) with varying voltage levels. A basic principle for selecting a snubber MOV is proposed based on the voltage ratio of a snubber and an energy-absorbing MOV. Finally, the feasibility of the proposed method is verified via a small-scale principle prototype.
41 citations
TL;DR: A resonant capacitive-coupling (RCC) approach for wireless power transfer to brain implants and is integrated with the Internet of Things (IoT) module for the remote monitoring and analyses of patient health.
Abstract: Neural implantable sensors require a harmless sustainable wireless power transfer technique for their lifetime operation. The capacitive-coupled (CC) power transfer method has proved to induce minimum electromagnetic interference as compared with inductive resonant power transfer. However, the CC method suffers from the limitation of low power transfer efficiency (PTE) and is suitable only for short-distance power transfer applications. In physical health-monitoring practices, the deep implants require high PTE with minimum electromagnetic interference. Similarly, the measured data need to be transmitted to the external world for remote monitoring and analysis. Nevertheless, the size and safety constraints limit the direct interfacing of the data communication module to implants. With this objective, this paper proposes a resonant capacitive-coupling (RCC) approach for wireless power transfer to brain implants. Moreover, to further improve the PTE, the proposed model is investigated with the additional intermediate plate capacitance between the transmitter (Tx) and the receiver (Rx). The analytical and experimental studies are carried out for intracranial pressure sensor (ICP) application and obtain the PTE of 24.2%, 34.14%, and 42.21% for CC, RCC, and RCC with an intermediate plate (RCCI) approaches, respectively. In addition, to eliminate the use of the antenna for data transfer, the same capacitive plates are used and tested with amplitude phase-shift keying (ASK) modulation technique for uplink communication. The proposed system is also integrated with the Internet of Things (IoT) module for the remote monitoring and analyses of patient health.
40 citations
TL;DR: This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology, a unique packaging paradigm that provides very high-density interconnects localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected.
Abstract: This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides very high-density interconnects (currently in the range of 500–1000 I/O/mm) localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected. The construction of the silicon bridge and the package to allow high BW electrical signaling between two dies is discussed in detail. Examples of the EMIB implementations for the links between the field-programmable gate array (FPGA) logic and high bandwidth memory generation 2 (HBM2) memory stacks, graphics die and HBM2 memory stacks, FPGA logic die, and high-performance transceiver die are described. EMIB packaging is compared with similar high-density interconnect technologies such as silicon interposer with through-silicon vias (TSVs) and other fan-out-based package technologies. Design optimization strategies for power delivery and I/O routing in the presence of an embedded bridge are highlighted.
40 citations
TL;DR: In this article, a substrate integrated waveguide bandpass filter (SIW BPF) is proposed, which is designed on the dielectric cavity that is etched on the traditional low resistivity silicon (LRSi) in a 3D IC system, acting as the insulating material between through-silicon via plugs and LRSi.
Abstract: This paper proposes a substrate integrated waveguide bandpass filter (SIW BPF), exploiting the through-dielectric via (TDV)-based 3-D integrated circuit (3-D IC) technology. The SIW BPF is designed on the dielectric cavity that is etched on the traditional low-resistivity silicon (LRSi) in a 3-D IC system, acting as the insulating material between through-silicon via plugs and LRSi. This construction can reduce prominent eddy current losses in LRSi and coupling losses among TDV plugs for the millimeter-wave application. Benzocyclobutene and glass are chosen as the dielectric cavity due to the low dielectric constant and loss tangent. The detailed design procedure beginning from the normalized Chebyshev low-pass filter to the final optimized SIW BPF is presented. The filter having a 12.5% fractional bandwidth is centered at 159.67 GHz. The return losses and insertion loss across the passband are about −10 and −1.5 dB, respectively. Numerical analysis of the advanced design system and full-wave simulation results of Ansoft’s HFSS show a good agreement.
38 citations
TL;DR: In this paper, a SiC power module using sintered Ag die attach with a direct-bonded-copper (DBC) substrate was designed and fabricated for reliable high-temperature operations.
Abstract: Silicon carbide (SiC) power modules with Ag sinter-bonding die attach were designed on the basis of thermal stress analysis for reliable high-temperature operations. Both the finite-element analysis (FEA) simulations and preliminary experiments confirmed that inserting the direct-bonded-copper (DBC) substrates can effectively reduce the maximum thermal stress in the module. A prototype SiC power module using sintered Ag die attach with a DBC substrate was designed and fabricated. The modules exhibited excellent durability in power cycling between 65 °C and 250 °C up to 20 000 cycles. FEA calculations of cumulative thermal strain and stress distributions adequately predicted the initial cracking position in the specimens after prolonged power cycles, observed by scanning electron microscopy.
36 citations
TL;DR: The proposed vision system is capable of controlling the entire robotic system while providing automatic rework capability on the defective solder joints with much less user interaction and has improved recognition rate and good resilience to noise and uneven illumination distribution.
Abstract: Machine vision has been widely deployed in many industrial applications. However, the accuracy and maturity level for the inspection of through-hole technology (THT) solder joints have yet to reach its ultimate goal. In this paper, we have presented a detailed explanation on a set of novel algorithms that can be effectively used to implement an automatic vision system that is capable of classifying the quality of THT solder joints very precisely. This vision system can be easily integrated into a soldering robotic system that performs automatic soldering on THT solder joints. The proposed vision system is capable of controlling the entire robotic system while providing automatic rework capability on the defective solder joints with much less user interaction. The experimental results indicate that the proposed system has an improved recognition rate and good resilience to noise and uneven illumination distribution.
TL;DR: In this article, the authors proposed an efficient method to suppress the crosstalk based on the mode mismatch between spoof surface plasmon polariton (SPP) transmission line (TL) and microstrip.
Abstract: We propose an efficient method to suppress the crosstalk based on the mode mismatch between spoof surface plasmon polariton (SPP) transmission line (TL) and microstrip. Since microstrip and spoof SPP TL support quasi-transverse electromagnetic (quasi-TEM) wave and transverse magnetic (TM) wave, respectively, the transmitting electromagnetic (EM) energy can hardly be coupled between these two kinds of TLs, which helps to reduce the crosstalk. For the cases of weak and strong coupling, two kinds of structures of spoof SPP TLs are designed. To verify the performance of crosstalk suppression, two samples of the coupled TLs are presented and fabricated. Simulated and experimental results show that the crosstalk of both strong and weak coupling is reduced by approximately 35 and 30 dB, respectively, by introducing the spoof SPP TL into the microstrip pair. Thus, crosstalk in traditional circuits can be alleviated by the mode mismatch between spoof SPP TLs and microstrips, which is significant for high-speed and high-density integrated systems.
TL;DR: In this paper, a hierarchical manifold microchannel design is presented that utilizes an integrated multilevel manifold distributor to feed coolant to an array of microchannel heat sinks, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures.
Abstract: High-heat-flux removal is critical for the next-generation electronic devices to reliably operate within their temperature limits. A large portion of the thermal resistance in a traditional chip package is caused by thermal resistances at interfaces between the device, heat spreaders, and the heat sink; embedding the heat sink directly into the heat-generating device can eliminate these interface resistances and drastically reduce the overall thermal resistance. Microfluidic cooling within the embedded heat sink improves the heat dissipation, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures. To enable multichip stacking and other heterogeneous packaging approaches, it is important to densely integrate all fluid flow paths into the device; volumetric heat dissipation emerges as a performance metric in this new heat sinking paradigm. In this paper, a compact hierarchical manifold microchannel design is presented that utilizes an integrated multilevel manifold distributor to feed coolant to an array of microchannel heat sinks. The flow features in the manifold layers and microchannels are fabricated in silicon wafers using deep reactive-ion etching. The heat source is simulated via Joule heating using thin-film platinum heaters. The on-chip spatial temperature measurements are made using four-wire resistance temperature detectors. The individual manifold layers and the microchannel-bearing wafers are diced and bonded into a sealed stack via thermocompression bonding using gold layers at the mating surfaces. Thermal and hydrodynamic testing is performed by pumping the dielectric fluid HFE-7100 through the device at a known flow rate, temperature, and pressure at different levels of chip heat input. A volumetric heat density of up to 2870 W/cm3 is dissipated at a chip temperature less than 112 °C and microchannel pressure drop less than 27 kPa. The overall pressure drop is governed by flowing through the manifold, rather than the microchannels, in this compact heat sink that occupies envelope of 5 mm $\times 5$ mm $\times2.3$ mm including all the functional flow features.
TL;DR: In this article, direct metal laser sintering was used to produce both straight and manifold microchannel designs with hydraulic diameters of $500~\mu \text{m}$ in an aluminum alloy (AlSi10Mg).
Abstract: Microchannel heat sinks allow the removal of dense heat loads from high-power electronic devices at modest chip temperature rises. Such heat sinks are produced primarily using conventional subtractive machining techniques or anisotropic chemical etching, which restricts the geometric features that can be produced. Owing to their layer-by-layer and direct-write approaches, additive manufacturing (AM) technologies enable more design-driven construction flexibility and offer improved geometric freedom. Various AM processes and materials are available, but their capability to produce features desirable for microchannel heat sinks has received a limited assessment. Following a survey of commercially mature AM techniques, direct metal laser sintering was used in this paper to produce both straight and manifold microchannel designs with hydraulic diameters of $500~\mu \text{m}$ in an aluminum alloy (AlSi10Mg). Thermal and hydraulic performances were characterized over a range of mass fluxes from 500 to 2000 kg/m2s using water as the working fluid. The straight microchannel design allows these experimental results to be directly compared against widely accepted correlations from the literature. The manifold design demonstrates a more complex geometry that offers a reduced pressure drop. A comparison of the measured and predicted performance confirms that the nominal geometry is reproduced accurately enough to predict pressure drop based on conventional hydrodynamic theory, albeit with roughness-induced early transition to turbulence; however, the material properties are not known with sufficient accuracy to allow for a priori thermal design. New design guidelines are needed to exploit the benefits of AM while avoiding undesired or unanticipated performance impacts.
TL;DR: In this paper, an optimized ultrathin gold (Au) layer of 3 nm has resulted in high-quality fine-pitch Cu-Cu thermocompression bonding at 140 °C and 0.3-MPa pressure.
Abstract: Optimally engineered ultrathin gold (Au) layer as an effective surface passivation for low-temperature, low-pressure fine-pitch Cu–Cu bonding is demonstrated in this paper. The Au passivation layer not only performs the role of protecting the underlying Cu surface from unwanted oxidation but it also helps in reducing the effective surface roughness, which are two major requirements for thermocompression bonding. In addition, Au, being a noble metal, ensures efficient surface passivation of Cu even at elevated temperatures. Furthermore, Au-passivated Cu surfaces show significantly high {111}-oriented surface planes with random grain structures at the bonding interface, which account for enhanced diffusion ability. Herein, an optimized Au passivation layer of 3 nm has resulted in high-quality fine-pitch Cu–Cu thermocompression bonding at 140 °C and 0.3-MPa pressure. The bonded samples have further been subjected to various reliability studies in order to confirm the efficacy of the proposed bonding scheme, along with mathematical modeling to cross check using Fick’s second law of approximation. The bonded samples have attributed to a high bond strength (>200 MPa) and a very low and stable specific contact resistance ( $\sim 1.43 \times 10^{\mathrm {-8}}\Omega $ cm $^{2}$ ) under robust conditions, which is significantly better than the values previously reported in the literature.
TL;DR: In this paper, the authors investigate the drop reliability of different solder joint microstructures using a coupled board-level finite element analysis and the microscale peridynamic (PD) simulations that can capture fracture in the heterogeneous solder joint.
Abstract: We investigate the drop reliability of different solder joint microstructures using a coupled board-level finite-element (FE) analysis and the microscale peridynamic (PD) simulations that can capture fracture in the heterogeneous solder joint. A new PD model for elastic behavior across a material interface is introduced and used in computing the damage and failure in the two-phase microstructure of a solder joint. This new model eliminates oscillations in strains at an interface. The microstructural geometry is digitized from the scanning electron microscopy images of experimentally tested samples. To simulate the drop test conditions, we employ the input acceleration method in the board-level FE model and calculate nodal velocities for the boundary conditions imposed on the microscale PD model. We test two different microstructures of intermetallic component (IMC) (AuSn4) and SAC305: flash and thick Au content. The results show significantly more fracture in the samples with larger Au content compared to the flash samples, which correlate well with experimental observations. The computed results show that the failure mechanism for solder joints with high Au content is a fracture through the AuSn4 IMC as well as along the interface between the inclusions and the matrix. A newly introduced measure, the quasi-damage index, estimates the locations in the microstructure of the solder joint with the highest risk for initiation of cracks and damage.
TL;DR: In this article, a single-phase high power electronics package is designed and developed, which achieves a significant thermal performance improvement compared with the conventional wire-bonded power package.
Abstract: A single-phase high power electronics package is designed and developed in this paper. The developed power package achieves a significant thermal performance improvement compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. First, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid-cooled heat sink attached to the bottom side of the AMB substrate is shortened. Hence, the thermal performance of the package is improved. Moreover, customized copper clips are introduced as the electrical interconnections between the SiC chips and the top metal layer of the substrate at the same level, and the top surface of the power package remain flat. As such another heat sink can be added to the top side of the package to further improve the thermal performance of the power package through the double-side cooling (DSC) scheme. The simulation results show that the junction-to-case thermal resistance (Theta JC) of the optimized power package is about 50% less than the Theta JC of the conventional wire-bonded power package with the same package size and the same power rate. Further applying the DSC scheme to the proposed power package, which is not suitable to the conventional wire-bonded power package, the Theta JC of the proposed power package reduces another 20%. In addition, the effects of the core layer (i.e., material and thickness) and the metal layer (i.e., materials and thicknesses) of the AMB substrate, as well as the die attach (i.e., material and thickness) on the Theta JC of the proposed power package are investigated systematically. As such the thermal performance of the power inverter package is further elaborated. Finally, the thermally enhanced power package is fabricated and assembled. Thermal characterization has been conducted, and the thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other.
TL;DR: In this article, a millimeter-scale liquid metal droplet thermal switch capable of controlling heat transfer spatially and temporally is presented, which can balance the device heat transfer rate and enhance junction temperature uniformity and system reliability.
Abstract: Heat dissipation is a key obstacle to achieving reliable, high-power-density electronic systems. Thermal devices capable of actively managing heat transfer are desired to enable heat dissipation optimization and enhanced reliability through device isothermalization. Here, we develop a millimeter-scale liquid metal droplet thermal switch capable of controlling heat transfer spatially and temporally. We demonstrate the thermal switch by integrating it with gallium nitride (GaN) devices mounted on a printed circuit board (PCB) and measure heat transfer and temperature of each device for a variety of switch positions and heat dissipation levels. When integrated with a single GaN device (2.6 mm $\times4.6$ mm face area) dissipating 1.8 W, the thermal switch shows the ability to actively control heat transfer by conducting 1.3 W in the ON mode with the GaN device at 51 °C ± 1 °C, and 0.5 W in the OFF mode with the GaN device at 95 °C ± 1 °C. To elucidate the heat transfer physics, we developed a 1-D system thermal resistance model in conjunction with an independent 3-D finite-element method (FEM) simulation, showing excellent agreement with our experimental data. Finally, we demonstrated that when the switch is integrated with two GaN devices, the switch can balance the device heat transfer rate and enhance junction temperature uniformity and system reliability by lowering the device-to-device temperature difference from > 10 °C (no switch) to 0 °C.
TL;DR: A fabrication approach for 3D printed waveguide paths based on a combination of an optimized electroless silver plating process with a waveguide-specific design rule for general metal plating by introducing large-scale non-radiating slots into the broad and narrow waveguide walls with a periodicity shorter than a quarter of the guided wavelength was proposed in this paper.
Abstract: This paper proposes a fabrication approach for 3-D printed waveguide paths based on a combination of an optimized electroless silver plating process with a waveguide-specific design rule for general metal plating by introducing large-scale non-radiating slots into the broad and narrow waveguide walls with a periodicity shorter than a quarter of the guided wavelength. Experimental fabrication of straight sections of the proposed slotted waveguide with various gap dimensions yields an optimum gap size as a result of a tradeoff between silver plating quality and leakage losses through the sidewall gaps. Moreover, a successful practical application of the proposed approach is presented in terms of a 3-D printed multiple bend waveguide interconnect in three different space dimensions, which imposes a complex task for conventional manufacturing techniques due to the need of multiple cutting planes for split block assembly. The proposed approach has the benefits of low cost, moderate handling effort, and independence of the concrete geometry to manufacture, making it, therefore, especially interesting for distribution and feeding networks in the context of rapid prototyping, automotive, and space-related applications.
TL;DR: In this article, a package concept based on low-temperature co-fired ceramic (LTCC) technology is illustrated for frequencies beyond 100 GHz, taking into consideration the inherent LTCC manufacturing defects, e.g., shrinkage, layer misalignment, and warping.
Abstract: In this paper, a package concept based on low-temperature cofired ceramic (LTCC) technology is illustrated. The concept is specifically designed for frequencies beyond 100 GHz, taking into consideration the inherent LTCC manufacturing defects, e.g., shrinkage, layer misalignment, and warping. Simple techniques are used for package assembly which can be automated using standard industrial processes. The proposed concept is implemented by integrating a 122-GHz silicon-germanium (SiGe) radar transceiver chip in an LTCC-based package. The off-chip components of the package, operating at 122 GHz, include a transmit (Tx) and a receive (Rx) aperture-coupled patch antenna array, a stripline to grounded coplanar waveguide signal transition feeding each of the antenna arrays, and three parallel, self-matched ground-signal-ground wirebonds connecting the SiGe radar transceiver chip and the LTCC package on Tx and Rx side. The simulation and measurement results of the Tx and Rx antenna arrays along with the signal transitions in the frequency range of 110–140 GHz are shown. The radar front end (RFE) is encapsulated using an epoxy molding compound, Polytec TC 430-T with suitable dielectric characteristics in the desired frequency range. The encapsulated RFE is surface mounted on a baseband printed circuit board, thereby realizing a fully functional 122-GHz frequency modulated continuous wave (FMCW) radar. The FMCW radar is used to measure the distance of a target, and the measurement results are compared with those of a commercial 122-GHz RFE.
TL;DR: The proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package and some advice on reducing warpage was given in the end.
Abstract: The fan-out package is designed to provide increased I/O density within a reduced form factor at a lower cost, as well as good electrical performance and heterogeneous integration capabilities, which has gained significant attention in recent years. However, warpage control during manufacturing process is a key character for fan-out packages. This paper focuses on the warpage prediction and optimization of embedded silicon fan-out (eSiFO) wafer-level package. An extended theoretical calculation model is applied and demonstrated, and the effects of various parameters on warpage were analyzed for optimization. By comparison with the experimental results, the finite-element modeling (FEM) simulation results and classic bimaterial model, the proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package. The effects of process steps, structural parameters, and material parameters were studied based on the extended theoretical model, and some advice on reducing warpage was given in the end. This paper offers an insight work for the warpage study of other embedded and fan-out packages.
TL;DR: In this paper, a quintuple-mode filter in one cavity is proposed by modifying a quarter-mode substrate-integrated waveguide (SIW) cavity, which is suitable for 3D integration of millimeter-wave and sub-terahertz transceiver systems.
Abstract: A novel quintuple-mode filter in one cavity is proposed by modifying a quarter-mode substrate-integrated waveguide (SIW) cavity. Modes can be independently controlled by dimension parameters of the resonator. The quintuple-mode resonator is packaged to prevent electromagnetic leakage, and pillars are added to remove spurious cavity resonances introduced by the packaging. A W-band filter is designed and fabricated by using benzocyclobutene (BCB) polymer as dielectrics. The microelectromechanical systems (MEMS) fabrication process is demonstrated in detail. This filter offers the advantages of easy integration with other active devices. It is suitable for 3-D integration of millimeter-wave and sub-terahertz transceiver systems. Four transmission zeros (TZs) are obtained to improve the stopband, and insertion loss is 1.97 dB at 89 GHz with a fractional bandwidth (FBW) of 22.5%. Simulated results agree with measured results.
TL;DR: In this article, a balanced bandpass filter (BPF), a balanced-to-balanced filtering power divider (FPD), and a balun filter are implemented using the isosceles right triangular patch element.
Abstract: In this paper, a balanced bandpass filter (BPF), a balanced-to-balanced filtering power divider (FPD), and a balun filter are implemented using the isosceles right triangular patch element. Two isosceles right triangular patch elements are coupled through an open stub for a triple-mode passband response under differential-mode operation and wide common-mode suppression simultaneously. To further improve the selectivity, an open stub is loaded on each feed-line. Based on these elements, a balanced BPF with excellent performance can be implemented. As an extension, a balanced-to-balanced FPD and a balun BPF are implemented based on the structure of the filter. For validation of the proposed configurations, all the balanced BPF, FPD, and balun BPF have been fabricated and measured. All measured results are found to be in a reasonable agreement with the simulation results.
TL;DR: In this article, microjets based on well-studied geometries were embedded within the substrate of a heat-producing device, removing several layers of thermal resistance typically found in advanced packages.
Abstract: With current trends toward increased power in smaller devices and packages, the search continues for high-performance thermal management solutions for MOSFETs, high-electron mobility transistors, and other power electronics. Microjet impingement cooling has been shown to produce high heat transfer capabilities for electronics cooling. In this paper, microjets based on well-studied geometries were embedded within the substrate of a heat-producing device, removing several layers of thermal resistance typically found in advanced packages. In contrast with competing liquid cooling solutions that use expensive materials and processes, industry-standard silicon microfabrication techniques were used to build a low-cost microjet cooler. Numerical analysis of the embedded microjet device showed average heat transfer coefficients greater than 250 kW/ $\text {m}^{2}\cdot \text {K}$ and low peak temperature rises in high power-density devices. Using an innovative micro-Raman thermography technique, experimental measurements with a 1- $\mu \text{m}$ spatial resolution were taken, supporting the numerically predicted heat transfer coefficients on a device with a heat flux of over 5 kW/cm2 and a temperature rise of 46 °C. As devices continue to become miniaturized, both low-cost embedded microjet cooling technology and micro-Raman thermography may play a vital role in the design, operation, and evaluation of advanced high power-density electronics.
TL;DR: In this paper, a high-temperature, W-band (75-110 GHz) free-space measurement system was developed and used to characterize complex dielectric properties of bulk material samples at temperatures ranging from 25 °C to 600 °C.
Abstract: Free-space measurement techniques can be contactless and are able to accommodate large, flat sheets of dielectric material, making them useful for characterization of high-temperature, millimeter-wave, window and radome candidate materials. As part of the present work, a high-temperature, W-band (75–110 GHz), free-space measurement system was developed and used to characterize complex dielectric properties of bulk material samples at temperatures ranging from 25 °C to 600 °C. Two test cases, polyvinyl chloride (PVC) and CoorsTek 92% alumina, were measured at 25 °C and found to have $\boldsymbol {\epsilon }_{r}^\prime $ values of 2.731 ± 0.005 and 8.061 ± 0.027 at 95 GHz, respectively. The 25 °C PVC sample was measured to have a $\boldsymbol {\epsilon }_{r}^{\prime \prime }$ value of 0.032 ± 0.007. At 25 °C, the $\boldsymbol {\epsilon }_{r}^{\prime \prime }$ value of the 92% alumina sample was below the uncertainty threshold achievable with the present free-space measurement apparatus and could only be bounded to $\boldsymbol {\epsilon }_{r}^\prime $ and $\boldsymbol {\epsilon }_{r}^{\prime \prime }$ values increased to 8.501 ± 0.028 and 0.035 ± 0.008, respectively. The high-temperature behavior of the authors’ 92% alumina ceramic was found to be similar to that previously documented for Sumitomo AKP-50 alumina over the 25 °C–600 °C temperature range. In addition to the 92% alumina sample, three commercially available ceramic substrates (zirconium oxide, boron nitride, and silicon nitride) were also characterized at temperatures ranging from 25 °C to 600 °C.
TL;DR: The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk.
Abstract: A multiobjective evolutionary method is proposed for the optimization of surface mount device (SMD) multilayer ceramic chip (MLCC) capacitors used for decoupling on printed circuit boards (PCBs) with resonant power–ground plane pairs. The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk. It is also shown that uniform MLCC capacitors with variable distance from power pins can have a similar decoupling effect to an assortment of capacitors. By simultaneously optimizing the pin-capacitor distance and value, the proposed method is shown to allow for the allocation of fewer decoupling capacitors under the ball-grid-array (BGA) pin field of an integrated circuit (IC) device.
TL;DR: In this article, an ANSYS simulation is performed to examine the warpage, extreme low- $k$ (ELK) interconnect stress and board-level solder joint reliability of the various package types.
Abstract: Fan-out (FO) packages are widely used in handheld, mobile consumer, and Internet of Things (IoT) devices due to the facility they provide for a greater I/O density and the integration of multiple components in a single package. Various types of FO package are available, including embedded wafer-level BGA (eWLB), fully molded (FM), and a flip-chip-based structure referred to as a fan-out chip-last package (FOCLP). In this paper, ANSYS simulations are performed to examine the warpage, extreme low- $k$ (ELK) interconnect stress and board-level solder joint reliability of the various package types. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the eWLB and FM packages with the experimental observations. Further simulations are then performed to investigate the heat dissipation performance and electrical crosstalk properties of the three packages. Taguchi experiments are conducted to examine the effects of eight control factors [namely, the inclusion (or otherwise) of a backside laminate film, the board thickness, the joint standoff distance, the ball joint diameter, the under bump metallurgy (UBM) diameter, the joint pitch, the die thickness, and the Cu pillar height] on the thermomechanical reliability of the FM package under accelerated thermal cycling testing. Finally, the Taguchi analysis results are used to determine the optimal geometry design of the FM package.
TL;DR: In this paper, an equivalent anisotropic thermal model is introduced to reduce the computational time resulting from complicated numerical integration, and the maximum deviation is less than 5%, indicating the accuracy of the proposed model.
Abstract: To investigate the thermal behavior of 3-D integrated circuits, long computational times are required for large-scale stacked chips with a complicated structure. In this paper, an equivalent anisotropic thermal model is introduced to reduce the computational time resulting from complicated numerical integration. By introducing the equivalent model, the complex nature of the through-silicon via (TSV) structure can be overcome. Our algorithm not only considers the anisotropic structure of the TSV and the orientation of the heat flux, but also considers the influence of the thermal coupling between TSVs. The finite-element method solver COMSOL is used for comparison with the proposed model, revealing a good agreement between the results of the simulation and the proposed models. The maximum deviation is less than 5%, indicating the accuracy of the proposed model, and the computational time of our model is reduced by 95.5%. In addition, parametric studies and studies of the structure are performed in order to further verify the accuracy of the proposed method and understand the main factors affecting the thermal behavior of a stacked 3-D chip.
TL;DR: In this article, an advanced electromagnetic-electrothermal analysis approach for the semiconductor power devices, with illustration on the insulated-gate bipolar transistor (IGBT) modules, is presented.
Abstract: We present in this paper an advanced electromagnetic (EM)-electrothermal analysis approach for the semiconductor power devices, with illustration on the insulated-gate bipolar transistor (IGBT) modules. This method distinguishes itself by dynamically integrating the EM domain into the circuit-type electrothermal coupling analysis, thus enabling the multi-dimensional simulation that spans in time from nanoseconds to seconds, and in space from chip level to system level. In particular, it contains a parametric-extracted electrothermal model of the IGBT chip and a comprehensive 0-D thermal network as well as an EM network extracted from the 3-D module packaging structure for each paralleling chip. The incorporation of the EM, as well as thermal networks representing the 3-D packaging structure, reveals essential information about the current imbalance, power dissipation imbalance, and thermal imbalance inside the IGBT module with paralleling chips, which have a strong influence on the module reliability. To demonstrate the application of this approach, an unfavorably designed 1700-V/450-A half-bridge IGBT power module is evaluated in the simulation circuit, with experimentally verified electrothermal IGBT chip model and thermal as well as EM networks. The results have shown that the EM-electrothermal analysis can successfully reveal the dynamic interaction among different physical domains and, thus, the current as well as temperature imbalance among the paralleling chips inside the power module. The predicted current imbalance also agrees with that from the experimental test.
TL;DR: In this paper, a new flow maldistribution mitigation technique is proposed, in which splitting of the single inlet port to the inlet manifold (conventional) into two separate inlet ports, and the results are compared with the conventional method.
Abstract: Flow rate nonuniformities (termed as maldistribution) among a stack of microchannels connected with each other through the inlet/outlet plenums of a microchannel heat sink (MCHS) are one of the major hindrances associated with effective and efficient operations. That induces many undesirable effects, including accentuation of lateral and flow direction nonuniformities in surface temperatures (for uniform heat flux loads). This can lead to feedback-induced lateral heat flow in the electronics underneath the MCHS, which is to be avoided. For the reported numerical study of single-phase liquid cooling, a new flow maldistribution mitigation technique—involving splitting of the single inlet port to the inlet manifold (conventional) into two separate inlet ports—is proposed, and the results are compared with the conventional method. The proposed scheme helps in reducing the flow maldistribution (its measure defined in this paper) problem. In the case of two ports, in the front of the inlet manifold, the reduction is about 26.2%, and in the case of one suitably placed port on each side of the inlet manifold, the flow rate maldistribution is reduced by about 68.5%, and in addition, the MCHS efficiency (defined as heat-carrying capacity per unit pumping power) is improved by 7.7%.