An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-mum CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than plusmn 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm2 of chip area excluding bondpads

A 95-dB linear low-power variable gain amplifier

This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

A monolithic low-power digitally programmable variable-gain amplifier (VGA) with a gain range of 75 dB is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor as well as tuning the resistors in the common-mode feedback circuitry. The overall VGA consists of three gain stages. As a proof of concept, a 24 dB single gain stage with 2 dB gain steps is fabricated in a 0.18 mum CMOS technology. Based on the measurement results of the prototype chip, the performance of the gain stage is optimized and a three-stage 75 dB VGA is designed and simulated. The overall gain can be varied from -15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz and the gain error is less than 0.3 dB. The overall VGA draws 6.5 mA from a 1.8 V supply. The noise figure of the system at maximum gain is 12.5 dB, and the IIP3 at minimum gain is 14.4 dBm.

A Low-Power 75dB Digitally Programmable CMOS Variable-Gain Amplifier

Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems. In this paper, a monolithic low-power digitally programmable VGA with 75 dB of gain range is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor and tuning the resistors in the common-mode feedback circuitry. The complete VGA consists of three gain stages. As a proof of concept, a 24 dB single-gain stage with 2 dB gain steps is fabricated in a 0.18 ?m CMOS technology. The prototype chip is tested, and measurement results are obtained. Based on these results, the gain stage is redesigned to optimize its performance, and a three-stage 75 dB VGA is designed and simulated. Each stage has a digitally tunable gain range of 25 dB. The overall gain can be varied from ?15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz, and the gain error is less than 0.3 dB. The overall VGA draws 6.5mA from a 1.8V power supply. The noise figure of the system at maximum gain is 12.5 dB, and the third-order intermodulation intercept point (IIP3) at minimum gain is 14.4 dBm.

A low-power 75 dB digitally programmable variable-gain amplifier in 0.18μm CMOS

A digitally-controlled topology that reduces power dissipation to half that of the conventional one while occupying smaller die area and obtaining higher linearity is presented. In the 0.13 µm CMOS process, the VGA occupies an active area of 0.46 mm2 and dissipates an average current of 5.2 mA at 1.5 V. The gain-variation range is −32 to 52 dB with a gain error of less than ±1 dB. The IIP3, P1dB, NF at 52 dB of gain, and 3 dB bandwidth are −37 to +13 dBm, −42 to −2 dBm, 6.2 dB and 200 MHz, respectively.

84 dB 5.2 mA digitally-controlled variable gain amplifier

A novel power reduction technique is proposed for a switched-capacitor amplifier (SCA) with two-stage operational amplifier. This technique improves both the bandwidth and the slew rate of the SCA with only two additional switches, and therefore, the power consumption of the SCA is reduced. This power reduction technique is applied to a variable gain amplifier (VGA) which is implemented in an analog front-end of camera modules for cellular phones. This reduces 30% of the VGA power consumption compared to the conventional one. Fabricated in 0.25-/spl mu/m CMOS process with 3.3-V transistors and MIM capacitors, the VGA occupies 0.49/spl times/0.49 mm/sup 2/ and dissipates 18.7 mW at 18 MHz with a supply voltage of 3.1 V.

H. Akada

Papers

A low-power switched-capacitor variable gain amplifier