This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-mum CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than plusmn 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm2 of chip area excluding bondpads

A 95-dB linear low-power variable gain amplifier

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 mum CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$ 98 dB THD

This paper describes a wideband high-linearity ?? ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled ?? ADC were realized in a 0.18-?m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR>100 dB, THD=-98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

A novel power reduction technique is proposed for a switched-capacitor amplifier (SCA) with two-stage operational amplifier. This technique improves both the bandwidth and the slew rate of the SCA with only two additional switches, and therefore, the power consumption of the SCA is reduced. This power reduction technique is applied to a variable gain amplifier (VGA) which is implemented in an analog front-end of camera modules for cellular phones. This reduces 30% of the VGA power consumption compared to the conventional one. Fabricated in 0.25-/spl mu/m CMOS process with 3.3-V transistors and MIM capacitors, the VGA occupies 0.49/spl times/0.49 mm/sup 2/ and dissipates 18.7 mW at 18 MHz with a supply voltage of 3.1 V.

A low-power switched-capacitor variable gain amplifier

A seventh-order single-loop single-bit delta-sigma modulator for a 1-bit digital audio switching amplifier is presented. To achieve high SNR and ensure the modulator stability for a large input range, the positions of the modulator loop filter poles and zeros are optimized, and a feedback comparator is used. A test chip was fabricated in a 0.35-μm CMOS process with optional 5-V transistors. The modulator achieves an SNR of 111 dB and 0.0015-% THD+N over the audio band. The normalized maximum allowable input range is 0.89. There are two modulators on one chip, one for each left and right audio channel. The isolation between both channels is over 135 dB. The chip area is 12.6 mm 2 and it draws 60 mA from a 5-V supply.

A delta-sigma modulator for a 1-bit digital switching amplifier

This paper describes the results of an implementation of a high speed DeltaSigma ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The DeltaSigma ADC is based on a switched-capacitor fourth-order single-loop DeltaSigma modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated DeltaSigma ADC and the digital signal processing block occupy 0.53 mm2 and 0.09 mm2, and consume 11.76 mW per channel.

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS

A seventh-order single-loop single-bit delta-sigma modulator for a 1-bit digital audio switching amplifier is presented. To achieve high SNR and ensure the modulator stability for a large input range, the positions of the modulator loop filter poles and zeros are optimized, and a feedback comparator is used. A test chip was fabricated in a 0.35-/spl mu/m CMOS process with optional 5-V transistors. The modulator achieves an SNR of 111 dB and 0.0015-% THD+N over the audio band. The normalized maximum allowable input range is 0.89. There are two modulators on one chip, one for each left and right audio channel. The isolation between both channels is over 135 dB. The chip area is 12.6 mm/sup 2/ and it draws 60 mA from a 5-V supply.

The design of a wideband low-power continuous-time (CT) delta-sigma modulator is presented in this paper. A modified feed-forward architecture is proposed to realize the low-power loop filter as well as cancel the out-of-band peaking in the signal transfer function. Several high-speed low-power design techniques are used in the circuits. The modulator achieves 60 dB dynamic range (DR) within 20 MHz signal bandwidth, and 55 dB DR within 25 MHz signal bandwidth. Clocked at 400 MHz, the modulator consumes only 10 mA current from a 1.8 V supply.

Yoshihisa Fujimoto

Papers

A low-power switched-capacitor variable gain amplifier

A delta-sigma modulator for a 1-bit digital switching amplifier

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS

A delta-sigma modulator for a 1-bit digital switching amplifier

A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications