The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.

Formation of silicided, ultra-shallow junctions using low thermal budget processing

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Publisher Summary This chapter provides a combined introductory overview and historical survey of the development of laser processing of semiconductors. It focuses on various types of lasers used for laser processing, other energy beam sources for processing, and laser processing of materials other than semiconductors. In the past, the irradiation of materials with high-powered lasers could lead to heating and cooling rates several orders of magnitude greater than those obtained by other means. However, the utilization of this aspect of lasers was inhibited by the small areas over which uniform energy densities could be obtained with lasers available at that time. With the gradual improvement in laser technology and the development of techniques for scanning beams over large areas, the interest in lasers for heat treating to obtain metallurgical modifications of the microstructure of materials has grown rapidly. The chapter discusses laser processing of insulators, ceramics, and glasses for semiconductors.

Chapter 1 Laser Processing of Semiconductors: An Overview

This paper presents a generalized electrical model of the interlayer contacts in integrated circuits and discusses various test structures capable of providing experimental data on the contacts. The techniques used for obtaining the specific contact resistance for the contacts and, where appropriate, the modification to conducting layer resistivities due to interactions Within the contact area are outlined. Using one of the techniques, experimental data on a polysilicon to single-crystal silicon contact is used as an example to obtain contact information. These results are discussed along with the experimental limitations applicable to the various techniques.

Determination of contact parameters of interconnecting layers in VLSI circuits

The amorphous to polycrystalline transformation of silicon implanted with high doses of In, Bi, Ga, and Sn is investigated. Each of these elements forms a low temperature eutectic with crystalline silicon and the details of the phase transformations in these systems are found to be very similar. A general model for the transformation based on the nature of the binary solutions is presented.

Amorphous to Polycrystalline Transformation in High Dose Ion Implanted Silicon

This review examines the annealing behaviour of ion implanted gallium arsenide during furance, laser and e-beam processing.The two annealing regimes, namely solid phase regrowth via furnace or CW laser/e-beam annealing and liquid phase epitaxy produced by pulsed lasers/e-beam, are examined in some detail.Emphasis is placed upon an understanding of the physical processes which are important during the various annealing modes.Comparison with the annealing behaviour of ion implantedelemental semiconductors(notably silicon) is made throughout the review to highlight relevant similarities and differences between compound and elemental semiconductors.The electrical properties of annealed gallium arsenide layers are not treatedin any detail, although particular observations which are relevant to the annealing processes are briefly discussed.

Transient and Furnace Annealing of Ion Implanted Gallium Arsenide

Undoped polycrystalline silicon (poly-Si) films obtained by low pressure chemical vapour deposition (LPCVD) techniques have previously been demonstrated to align epitaxially with respect to the underlying (100) silicon substrate in the 1000–1100°C temperature regime. However the alignment rate at temperatures in excess of 1100°C is too rapid to be obtained by conventional furnace processing. Rapid Thermal Processing (RTP) offers an excellent technique of attaining this temperature in the requisite time and in this paper we report on the results of a study in which RTP has been used. Our results show an activation energy of ∼4.5eV, and that the growth rate constant is dramatically enhanced, without any alignment delay in the initial heat treatment phase, which is contrary to previous findings.

Using Rapid Thermal Processing to Induce Epitaxial Alignment of Polycrystalline Silicon Films on (100) Silicon

An integral part of very large scale integrated (VLSI) circuits is the multilayer structures for electrical interconnection and insulation. Many conducting materials are used for interconnection including polysilicon, silicon, silicides, polycides and metals. An important point in considering these materials is the interconnection between them and the corresponding characterization of the interface by way of the specific contact resistance, which directly affects the interfacial contact resistance. For a planar ohmic contact formed between a metal and any layer with a much larger sheet resistance (for example single crystal silicon) a technique based on the transmission line model provides a method of characterizing these contacts. However, for planar contacts between layers with comparable sheet resistivities for example polysilicon to single crystal silicon this technique must be modified. In this paper we review the transmission line approach used to obtain the specific contact resistance between such layers and provide initial results of measurements made on the poly to single crystal interface. We also present a series of test structures, currently under fabrication that will provide more detailed experimental data.

Specific Contact Resistance Measurements on Multilayer Interconnect Structures

A detailed characterisation of rapid thermally annealed BF2+ and B+ implanted silicon has been carried out using the complementary techniques of in line 4 point probe and Van der Pauw electrical measurements, transmission electron microscopy, Rutherford backscattering/channeling and secondary ion mass spectrometry. Our results after rapid thermal annealing indicate that defect trapping and release of boron strongly influence both the diffusion behaviour and the electrical properties of the samples.

Characterisation of BF2+ and B+implanted silicon after rapid thermal annealing

Following the implantation of arsenic into titanium disilicide films on p type silicon, Rutherford backscattering has shown that rapid thermal vacuum processing (RTVP) causes the arsenic to diffuse toward the silicide/silicon interface, with an accumulation at the interface and with a sharp shallow diffusion into the silicon. The effect of the implant and anneal on the sheet resistance of the silicide and underlying silicon have been investigated’ and it is shown that anneal times of thirty seconds at 900 °C produce acceptable shallow junctions suitable for device type applications without significant deterioration in silicide electrical or physical properties.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400531959

H.B. Harrison

Papers

Transient and Furnace Annealing of Ion Implanted Gallium Arsenide

Using Rapid Thermal Processing to Induce Epitaxial Alignment of Polycrystalline Silicon Films on (100) Silicon

Specific Contact Resistance Measurements on Multilayer Interconnect Structures

Characterisation of BF2+ and B+implanted silicon after rapid thermal annealing

Shallow Junctions Formed by the Thermal Redistribution of Implanted Arsenic into TiSi2