We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

/pdf/the-fundamental-downscaling-limit-of-field-effect-5afj7tfrox.pdf

The fundamental downscaling limit of field effect transistors

FinFET is a multiple-gate silicon transistor structure that nowadays is attracting an extensive attention to progress further into the nanometer era by going beyond the downscaling limit of the conventional planar CMOS technology. Although the interest for this architecture has been mainly devoted to digital applications, the analysis at high frequency is crucial for targeting a successful mixed integration of analog and digital circuits. In view of that, the purpose of this review paper is to provide a clear and exhaustive understanding of the state of art, challenges, and future trends of the FinFET technology from a microwave modeling perspective. Inspired by the traditional modeling techniques for conventional MOSFETs, different strategies have been proposed over the last years to model the FinFET behavior at high frequencies. With the aim to support the development of this technology, a comparative study of the achieved results is carried out to gain both a useful feedback to investigate the microwave FinFET performance as well as a valuable modeling know-how. To accomplish a comprehensive review, all aspects of microwave modeling going from linear (also noise) to non-linear high-frequency models are addressed.

A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do face certain special challenges, particularly with respect to the process-induced variations in the following: 1) the channel length and 2) the thickness of the silicon thin film and gate oxide. This paper, for the first time, studies the impact of the aforementioned process variations on the electrical characteristics of a double-gate tunnel field-effect transistor (DGTFET). Using 2-D device simulations, we propose the strained DGTFET as a possible solution for effectively compensating the process-induced variations in the on-current, threshold voltage, and subthreshold swing and improving the reliability of the DGTFET.

https://web.iitd.ac.in/~mamidala/HTMLobj-1383/Sneh-TDMR.pdf

Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability

We present a methodology to calculate the formation energy of a charged defect at a surface, an interface, or a two-dimensional material in the presence of a macroscopic electric field. We demonstrate that the proposed formalism corrects for electrostatic artifacts in standard repeated-slab calculations and allows us to extract reliably the formation energy in the isolated defect limit independently of vacuum thickness, slab thickness, or lateral supercell size. The formalism does not enter the self-consistency loop of a density functional theory (DFT) calculation, but requires as input only the electrostatic potential of the converged calculation. Thus, employing the proposed scheme does not require any changes in the DFT code, but only a postprocessing module that we provide for various codes.

First-principles calculations for charged defects at surfaces, interfaces, and two-dimensional materials in the presence of electric fields

The influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field-effect transistors is numerically investigated using a full 3-D quantum transport simulator based on an atomistic sp3d5s* tight-binding model. An interface between silicon and silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function. An oxide layer is modeled in a virtual crystal approximation using fictitious SiO2 atoms. 〈110〉-oriented NWs with different diameters and randomly generated surface configurations are studied. An experimentally observed on-current and threshold voltage are quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental data.

Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied

Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

Semiconductor Device Modeling

We utilized a fully self-consistent quantum mechanical simulator based on the contact block reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO2 gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

We examined the influence of process variation on device performance of the optimized 10-nm FinFET device using a fully self-consistent quantum-mechanical transport simulator based on the contact block reduction method. Sensitivity of the on-current, leakage currents, threshold voltage, drain-induced barrier lowering, and subthreshold swing for the optimized FinFET to process variation at room temperature have been investigated. Subthreshold source-to-drain leakage current is found to be the most sensitive parameter to process variation. Gate leakage current has been analyzed for both poly-Si gates and gates with the work function of 4.35 eV. For poly-Si gates, the gate leakage is found to influence the subthreshold swing below or at a gate oxide thickness of 1 nm. Device performance has also been analyzed at ldquoslow processrdquo corner to estimate the worst case degradation in performance matrices of the considered nano-FinFET.

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET

In state of the art devices, it is well known that quantum and Coulomb effects play significant role on the device operation. In this book chapter we demonstrate that a novel effective potential approach in conjunction with a Monte Carlo device simulation scheme can accurately capture the quantum-mechanical size quantization effects. Inclusion of tunneling within semi-classical simulation schemes is discussed in details. We also demonstrate, via proper treatment of the short-range Coulomb interactions, that there will be significant variation in device design parameters for devices fabricated on the same chip due to the presence of unintentional dopant atoms at random locations within the channel of alternative technology devices.

/pdf/quantum-and-coulomb-effects-in-nanodevices-1bcrj9uc9v.pdf

H. Khan

Papers

Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

Semiconductor Device Modeling

Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET

Quantum and Coulomb Effects in Nanodevices