Showing papers in "IEEE Transactions on Electron Devices in 2007"

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation

Abstract: We have developed a normally-off GaN-based transistor using conductivity modulation, which we call a gate injection transistor (GIT). This new device principle utilizes hole-injection from the p-AlGaN to the AlGaN/GaN heterojunction, which simultaneously increases the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation. The fabricated GIT exhibits a threshold voltage of 1.0 V with a maximum drain current of 200 mA/mm, in which a forward gate voltage of up to 6 V can be applied. The obtained specific ON-state resistance (RON . A) and the OFF-state breakdown voltage (BV ds) are 2.6 mOmega . cm2 and 800 V, respectively. The developed GIT is advantageous for power switching applications.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

Abstract: This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large-(digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET-device model incorporating the additional device/circuit-level non-idealities and multiple CNTs reported in the paper of Deng and Wong.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Abstract: This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

nextnano: General Purpose 3-D Simulations

Abstract: nextnano is a semiconductor nanodevice simulation tool that has been developed for predicting and understanding a wide range of electronic and optical properties of semiconductor nanostructures. The underlying idea is to provide a robust and generic framework for modeling device applications in the field of nanosized semiconductor heterostructures. The simulator deals with realistic geometries and almost any relevant combination of materials in one, two, and three spatial dimensions. It focuses on an accurate and reliable treatment of quantum mechanical effects and provides a self-consistent solution of the Schrodinger, Poisson, and current equations. Exchange-correlation effects are taken into account in terms of the local density scheme. The electronic structure is represented within the single-band or multiband kldrp envelope function approximation, including strain. The code is not intended to be a ldquoblack boxrdquo tool. It requires a good understanding of quantum mechanics. The input language provides a number of tools that simplify setting up device geometry or running repetitive tasks. In this paper, we present a brief overview of nextnano and present four examples that demonstrate the wide range of possible applications for this software in the fields of solid-state quantum computation, nanoelectronics, and optoelectronics, namely, 1) a realization of a qubit based on coupled quantum wires in a magnetic field, 2) and 3) carrier transport in two different nano-MOSFET devices, and 4) a quantum cascade laser.

Magnetic Tunnel Junctions for Spintronic Memories and Beyond

Abstract: In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (Rp) or high (Rap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (Rap $Rp)/Rp as high as 361%, have been obtained in MTJs with Co40Fe40B20 fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (JCO) on the order of 106 A/cm2 in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced JCO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low JCO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture

Bipolar and Unipolar Resistive Switching in Cu-Doped $ \hbox{SiO}_{2}$

Abstract: Scalable nonvolatile memory devices that operate at low voltage and current, exhibit multilevel cell capability, and can be read nondestructively using simple circuitry, are highly sought after. Such devices are of particular interest if they are compatible with back-end-of-line processing for CMOS integrated circuits. A variety of resistance-change technologies show promise in this respect, but a new approach that is based on switching in copper-doped silicon dioxide may be the simplest and least expensive to integrate. This paper describes the characteristics of W-(Cu/SiO2)-Cu programmable metallization cell (PMC) devices formed by the thermal diffusion of Cu into deposited SiO2. PMC devices operate by the electrochemical control of metallic pathways in solid electrolytes. Both unipolar and bipolar resistive switching could be attained in these devices. Bipolar switching, which is identical to that seen in PMC devices based on other solid electrolytes, was observed for low bias (a few tenths of volts) and programming currents in the microampere range. The resistance ratio between high and low states was on the order of 103, and a multibit storage is considered possible via the strong dependence of ON-state resistance on programming current. The low and high resistance states were stable for more than 5 x 104 s. The devices could be made to exhibit unipolar switching using a negative bias on the order of -1 V combined with erase currents of hundreds of microampere to a few milliampere. In this case, the OFF/ON ratio was 106.

Design Considerations of Silicon Nanowire Biosensors

Abstract: Biosensors based on silicon nanowires (Si-NWs) promise highly sensitive dynamic label-free electrical detection of biomolecules. Despite the tremendous potential and promising experimental results, the fundamental mechanism of electrical sensing of biomolecules and the design considerations of NW sensors remain poorly understood. In this paper, we discuss the prospects and challenges of biomolecule detection using Si-NW biosensors as a function of device parameters, fluidic environment, charge polarity of biomolecules, etc., and refer to experimental results in literature to support the nonintuitive predictions wherever possible. Our results indicate that the design of Si nanobiosensor is nontrivial and as such, only careful optimization supported by numerical simulation would ensure optimal sensor performance.

Oxide Spintronics

Abstract: Concomitant with the development of metal-based spintronics in the late 1980s and 1990s, important advances were made on the growth of high-quality oxide thin films and heterostructures. While this was at first motivated by the discovery of high-temperature superconductivity in perovskite Cu oxides, this technological breakthrough was soon applied to other transition-metal oxides and, notably, mixed-valence manganites. The discovery of colossal magnetoresistance in manganite films triggered intense research activity on these materials, but the first notable impact of magnetic oxides in the field of spintronics was the use of such manganites as electrodes in magnetic tunnel junctions, yielding tunnel magnetoresistance ratios that are one order of magnitude larger than what had been obtained with transition-metal electrodes. Since then, research on oxide spintronics has been intense, with the latest developments focused on diluted magnetic oxides and, more recently, on multiferroics. In this paper, the most important results on oxide spintronics was reviewed, emphasizing materials physics as well as spin-dependent transport phenomena, and finally give some perspectives on how the flurry of new magnetic oxides could be useful for next-generation spintronics devices

Short-Channel Effect Limitations on High-Frequency Operation of AlGaN/GaN HEMTs for T-Gate Devices

Abstract: AlGaN/GaN high-electron mobility transistors (HEMTs) were fabricated on SiC substrates with epitaxial layers grown by multiple suppliers and methods. Devices with gate lengths varying from 0.50 to 0.09 mum were fabricated on each sample. We demonstrate the impact of varying the gate lengths and show that the unity current gain frequency response (fT) is limited by short-channel effects for all samples measured. We present an empirically based physical model that can predict the expected extrinsic fT for many combinations of gate length and commonly used barrier layer thickness (tbar) on silicon nitride passivated T-gated AlGaN/GaN HEMTs. The result is that even typical high-aspect-ratio (gate length to barrier thickness) devices show device performance limitations due to short-channel effects. We present the design tradeoffs and show the parameter space required to achieve optimal frequency performance for GaN technology. These design rules differ from the traditional GaAs technology by requiring a significantly higher aspect ratio to mitigate the short-channel effects.

Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories

Abstract: The electronic behavior of the chalcogenide material used in phase-change memory (PCM) plays a key role in defining the operation voltages and times of the memory cell. In particular, the threshold voltage for electronic switching of the amorphous chalcogenide determines the boundary between programming and readout operation, while its resistance allows the recognition of the bit status. This paper present a time-resolved analysis of threshold voltage and resistance in a PCM. Both dynamics of threshold voltage and resistance display a fast transient, named recovery behavior, in the first 30 ns after programming. A slower, nonsaturating drift transient is found for longer times. The two transients are discussed referring to electronic and structural rearrangements in the amorphous chalcogenide. Finally, the impact on the device level is considered

Performance Projections for Ballistic Graphene Nanoribbon Field-Effect Transistors

Abstract: The upper limit performance potential of ballistic carbon nanoribbon MOSFETs (CNR MOSFETs) is examined. Calculation of the bandstructure of nanoribbons using a single pz-orbital tight-binding method and evaluation of the current-voltage characteristics of a nanoribbon MOSFET were used in a semiclassical ballistic model. The authors find that semiconducting ribbons a few nanometers in width behave electronically in a manner similar to carbon nanotubes, achieving similar ON-current performance. The calculations show that semiconducting CNR transistors can be candidates for high-mobility digital switches, with the potential to outperform the silicon MOSFET. Although wide ribbons have small bandgaps, which would increase subthreshold leakage due to band to band tunneling, their ON-current capabilities could still be attractive for certain applications

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Abstract: Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm2 cross-sectional area

Thermal Boundary Resistance Between GaN and Substrate in AlGaN/GaN Electronic Devices

Abstract: The influence of a thermal boundary resistance (TBR) on temperature distribution in ungated AlGaN/GaN field-effect devices was investigated using 3-D micro-Raman thermography. The temperature distribution in operating AlGaN/GaN devices on SiC, sapphire, and Si substrates was used to determine values for the TBR by comparing experimental results to finite-difference thermal simulations. While the measured TBR of about 3.3 x 10-8 W-1 ldr m2 ldr K for devices on SiC and Si substrates has a sizeable effect on the self-heating in devices, the TBR of up to 1.2 x 10-8 W-1 ldr m2 ldr K plays an insignificant role in devices on sapphire substrates due to the low thermal conductivity of the substrate. The determined effective TBR was found to increase with temperature at the GaN/SiC interface from 3.3 x 10-8 W-1 ldr m2 ldr K at 150degC to 6.5 x 3.3 x 10-8 W-1 ldr m2 ldr K at 275degC, respectively. The contribution of a low-thermal-conductivity GaN layer at the GaN/substrate interface toward the effective TBR in devices and its temperature dependence are also discussed.

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

Abstract: Recent advances in experimental techniques (on-the- fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale Such measurements over wider temperature range (-25degC to 145degC), film thicknesses (12-22 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes

Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D—Part I: Models and Benchmarks

Abstract: Device physics and material science meet at the atomic scale of novel nanostructured semiconductors, and the distinction between new device or new material is blurred. Not only the quantum-mechanical effects in the electronic states of the device but also the granular atomistic representation of the underlying material are important. Approaches based on a continuum representation of the underlying material typically used by device engineers and physicists become invalid. Ab initio methods used by material scientists typically do not represent the band gaps and masses precisely enough for device design, or they do not scale to realistically large device sizes. The plethora of geometry, material, and doping configurations in semiconductor devices at the nanoscale suggests that a general nanoelectronic modeling tool is needed. The 3-D NanoElectronic MOdeling (NEMO 3-D) tool has been developed to address these needs. Based on the atomistic valence force field and a variety of nearest neighbor tight-binding models (e.g., s, sp3s*, and sp3d5s*), NEMO 3-D enables the computation of strain and electronic structure for more than 64 and 52 million atoms, corresponding to volumes of (110 nm)3 and (101 nm)3, respectively. The physical problem may involve very large scale computations, and NEMO 3-D has been designed and optimized to be scalable from single central processing units to large numbers of processors on commodity clusters and supercomputers. NEMO 3-D has been released with an open-source license in 2003 and is continually developed by the Network for Computational Nanotechnology (NCN). A web-based online interactive version for educational purposes is freely available on the NCN portal ( http://www.nanoHUB.org). In this paper, theoretical models and essential algorithmic and computational components that have been used in the development and successful deployment of NEMO 3-D are discussed.

Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices

Abstract: In this paper, the transient analysis of an AlGaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor-type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities >1e20 cm-3 (>5e12 cm-2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states

Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

Abstract: The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R on Q gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.

The Effect of General Strain on the Band Structure and Electron Mobility of Silicon

Abstract: A model capturing the effect of general strain on the electron effective masses and band-edge energies of the lowest conduction band of silicon is developed. Analytical expressions for the effective mass change induced by shear strain and valley shifts/splittings are derived using a degenerate kldrp theory at the zone-boundary X point. Good agreement to numerical band- structure calculations using the nonlocal empirical pseudopotential method with spin-orbit interactions is observed. The model is validated by calculating the bulk electron mobility under general strain with a Monte Carlo technique using the full-band structure and the proposed analytical model for the band structure. Finally, the impact of strain on the inversion-layer mobility of electrons is discussed.

Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators

Abstract: A large-area, flexible, and lightweight sheet-type Braille display has been successfully fabricated on a plastic film by integrating high-quality organic transistors and soft actuators. An array of rectangular plastic actuators is mechanically processed from a perfluorinated polymer electrolyte membrane. A small semisphere, which projects upward from the rubberlike surface of the display, is attached to the tip of each rectangular actuator. The effective display size is 4times4 cm2. Each Braille letter consists of 3times2 dots and 24 letters; in other words, 6 letters times 4 lines can be displayed. Pentacene field-effect transistors with top-contact geometry have a channel length of 20 mum and a mobility of 1 cm2/Vmiddots. The Braille dots on one line are driven for 0.9 s. The total thickness and weight of the entire device are 1 mm and 5.3 g, respectively. The present scheme will enable people with visual impairments to carry the Braille sheet display in their pockets and read Braille e-books at any time. Since all the device components are manufactured on plastic films, these sheet-type Braille displays are mechanically flexible, lightweight, shock resistant, and potentially inexpensive to manufacture; therefore, they are suitable for mobile electronics

Design of Highly Efficient Light-Trapping Structures for Thin-Film Crystalline Silicon Solar Cells

Abstract: We present a design optimization of a highly efficient light-trapping structure to significantly increase the efficiency of thin-film crystalline silicon solar cells. The structure consists of an antireflection (AR) coating, a silicon active layer, and a back reflector that combines a diffractive reflection grating with a distributed Bragg reflector. We have demonstrated that with careful design optimization, the presented light-trapping structure can lead to a remarkable cell-efficiency enhancement for the cells with very thin silicon active layers (typically 2.0-10.0 mum) due to the significantly enhanced absorption in the wavelength range of 800-1100 nm. On the other hand, less enhancement has been predicted for much thicker cells (i.e.,>100 mum) due to the limited absorption increase in this wavelength range. According to our simulation, the overall cell efficiency can be doubled for a 2.0-mum-thick cell with light-trapping structure. It is found that the improvement is mainly contributed by the optimized AR coating and diffraction grating with the corresponding relative improvements of 36% and 54%, respectively. The simulation results show that the absolute cell efficiency of a 2.0-mum-thick cell with the optimal light-trapping structure can be as large as 12%.

Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs

Abstract: A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI) MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The matrix element of the scattering potential reflects the fluctuations of both the wavefunction and the potential energy. The matrix element reflecting the fluctuation of the wavefunction is expressed in an integral form which can be considered as a generalized Prange-Nee term-to which it is equivalent in the limit of an infinitely high insulator-semiconductor barrier-giving more accurate results in the case of a finite barrier height. The matrix element reflecting the fluctuation of the potential energy is due to the Coulomb interactions originating from the roughness-induced fluctuation of the electron charge density, the interface polarization charge, and the image-charge density. The roughness-limited low-field electron mobility in thin-body SOI MOSFETs is obtained using the matrix elements that we have derived. We study its dependence on the silicon body thickness, effective field, and dielectric constant of the insulator.

Nonequilibrium Green's Function Treatment of Phonon Scattering in Carbon-Nanotube Transistors

Abstract: We present a detailed treatment of dissipative quantum transport in carbon-nanotube field-effect transistors (CNT-FETs) using the nonequilibrium Green's function formalism. The effect of phonon scattering on the device characteristics of CNT-FETs is explored using extensive numerical simulation. Both intra- and intervalley scattering mediated by acoustic (AP), optical (OP), and radial-breathing-mode (RBM) phonons are treated. Realistic phonon dispersion calculations are performed using force- constant methods, and electron-phonon coupling is determined through microscopic theory. Specific simulation results are presented for (16,0), (19,0), and (22,0) zigzag CNTFETs, which are in the experimentally useful diameter range. We find that the effect of phonon scattering on device performance has a distinct bias dependence. Up to moderate gate biases, the influence of high-energy OP scattering is suppressed, and the device current is reduced due to elastic backscattering by AP and low-energy RBM phonons. At large gate biases, the current degradation is mainly due to high-energy OP scattering. The influence of both AP and high-energy OP scattering is reduced for larger diameter tubes. The effect of RBM mode, however, is nearly independent of the diameter for the tubes studied here.

Enhancing the Near-Infrared Spectral Response of Silicon Optoelectronic Devices via Up-Conversion

Abstract: A silicon-based optoelectronic device that exhibits an enhanced response to subbandgap light is described. The device structure consists of a bifacial silicon solar cell with an up- converting (UC) layer attached to the rear. Erbium-doped sodium yttrium fluoride (NaY0.8F4 : Er0.2 3+) phosphors are the optically active centers responsible for the UC luminescence. The unoptimized device is demonstrated to respond effectively to wavelengths (lambda) in the range of 1480-1580 nm with an external quantum efficiency (EQE) of 3.4% occurring at 1523 nm at an illumination intensity of 2.4 W/cm2 (EQE = 1.4 times 10-2 cm2/W). An analysis of the optical losses reveals that the luminescence quantum efficiency (LQE) of the device is 16.7% at 2.4 W/cm2 of 1523-nm excitation (LQE = 7.0 times 10-2 cm2/W), while further potential device improvements indicate that an EQE of 14.0% (5.8 times 10-2 cm2/W) could be realistically achieved.

Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study

Abstract: The scaling behaviors of graphene nanoribbon (GNR) Schottky barrier field-effect transistors (SBFETs) are studied by self-consistently solving the nonequilibrium Green's function transport equation in an atomistic basis set with a 3-D Poisson equation. The armchair edge GNR channel shares similarities with a zigzag carbon nanotube; however, it has a different geometry and quantum confinement boundary condition in the transverse direction. The results indicate that the I-V characteristics are ambipolar and strongly depend on the GNR width because the bandgap of the GNR is approximately inversely proportional to its width, which agrees with recent experiments. A multiple gate geometry improves immunity to short channel effects; however, it offers smaller improvement than it does for Si MOSFETs in terms of the on-current and transconductance. Reducing the oxide thickness is more useful for improving transistor performance than using a high-k gate insulator. Significant increase of the minimal leakage current is observed when the channel length is scaled below 10 nm because the small effective mass facilitates strong source-drain tunneling. The GNRFET, therefore, does not promise to extend the ultimate scaling limit of Si MOSFETs. The intrinsic switching speed of a GNR SBFET, however, is several times faster than that of Si MOSFETs, which could lead to promising high-speed electronics applications, where the large leakage of GNR SBFETs is of less concern.

Impact of Line-Edge Roughness on FinFET Matching Performance

Abstract: As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.

ZnO Doped With Transition Metal Ions

Abstract: Spin-dependent phenomena in ZnO may lead to devices with new or enhanced functionality, such as polarized solid-state light sources and sensitive biological and chemical sensors. In this paper, we review the experimental results on transition metal doping of ZnO and show that the material can be made with a single phase at high levels of Co incorporation (~15 at.%) and exhibits the anomalous Hall effect. ZnO is expected to be one of the most promising materials for room-temperature polarized light emission; but to date, we have been unable to detect the optical spin polarization in ZnO. The short spin relaxation time observed likely results from the Rashba effect. Possible solutions involve either cubic phase ZnO or the use of additional stressor layers to create a larger spin splitting in order to get a polarized light emission from these structures or to look at alternative semiconductors and fresh device approaches

Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs

Abstract: Explicit continuous models for both double-gate (DG) and surrounding-gate (SG) MOSFETs are presented. These models evolve from previous DG and SG MOSFETs models, which need to solve implicit equations for intermediate parameters by numerical iteration or the table lookup method. By developing approximate explicit solutions for the intermediate parameters, we can express the drain current, terminal charge, transconductance, and transcapacitance as explicit functions of applied voltages as well as the structural parameters. High accuracy and efficiency, combined with inherited favorable features from the previous models, make these new models suitable for circuit simulation programs.

Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture

Abstract: In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level and the doping nonuniformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled ldquorealisticrdquo bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

Semiconductors Between Spin-Polarized Sources and Drains

Abstract: Injecting spins into a semiconductor channel and transforming the spin information into a significant electrical output signal is a long-standing problem in spintronics. This is the prerequisite of several concepts of spin transistor. In this paper, we discuss the general problem of spin transport in a nonmagnetic channel between source and drain. Two problems must be mastered: 1) In diffusive regime, the injection/extraction of a spin-polarized current into/from a semiconductor beyond the ballistic zone at the interface with a magnetic metal requires the insertion of a spin-dependent and large enough interface resistance. 2) In both the diffusive and ballistic regimes and whatever the metallic or semiconducting character of the source/drain, a small enough interface resistance is the condition to keep the dwell time shorter than the spin lifetime and, thus, to conserve the spin-accumulation-induced output signal at an optimum level (DeltaR/Rap1 or larger). Practically, the main difficulties come from the second condition. In our presentation of experimental results, we show why the transformation of spin information into a large electrical signal has been more easily achieved with carbon nanotubes than with semiconductors, and we discuss how the situation could be improved in the later case