This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.

https://web.iitd.ac.in/~mamidala/HTMLobj-160/april04.pdf

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

https://web.iitd.ac.in/~mamidala/HTMLobj-248/March05NANO.pdf

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

Dual-material gate (DMG) field effect transistor

High‐performance bilayer In2O3/IGZO thin‐film transistors (TFTs) fabricated by pulsed laser deposition are reported. The TFTs exhibit an on/off current ratio of 109, a reversed subthreshold slope (ss) of 0.08 V dec−1, and a high saturation mobility of 47.9 cm2 V−1 s−1. The reliability of the mobility values is critically validated and assessed by four‐probe measurements, the transfer‐length method, and the temperature‐dependence. X‐ray photoelectron spectra are combined with C–V measurements to characterize the interface, and the results show that a two‐dimensional electron gas (2DEG)‐like state accumulates at the In2O3/IGZO interface. However, this state only forms in the subthreshold region and does not cause the high carrier mobility in the region above the threshold. Instead, the enhanced carrier mobility results from the intrinsic high mobility of the In2O3, the smooth surface, and the low‐defect states in the In2O3/IGZO bilayer with a good percolation transport path.

Critical Assessment of the High Carrier Mobility of Bilayer In2O3/IGZO Transistors and the Underlying Mechanisms

https://doi.org/10.1016/j.isci.2022.105164

A multimode photodetector with polarization-dependent near-infrared responsivity using the tunable split-dual gates control

High-voltage thin-film transistors (HV-TFTs) with designed field-plates are experimentally demonstrated to work in a wide range of kilo-voltage (kV) and with the tunable breakdown voltages (<inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BD}}}$ </tex-math></inline-formula>). The field plates have been placed in different positions and biased at different voltages to investigate how to effectively enhance <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BD}}}$ </tex-math></inline-formula>. The largest <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BD}}}$ </tex-math></inline-formula> is up to 263 % of the case without field plate and reaches 1902.5 V. By monitoring the electric potential at the end of the gated channel (<inline-formula> <tex-math notation="LaTeX">${V}_{1}$ </tex-math></inline-formula>), it is revealed that the enhanced <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BD}}}$ </tex-math></inline-formula> is associated with a reduced <inline-formula> <tex-math notation="LaTeX">${V}_{1}$ </tex-math></inline-formula>. Therefore, the device breakdown is in fact caused by the breakdown of dielectric near the end of the gated channel in HV-TFTs rather than the destruction of semiconductor near the drain in regular TFTs. This study unveils the breakdown mechanisms of HV-TFTs and provides an effective design route for balancing the breakdown voltages and on-current of the HV-TFTs.

Widely Adjusting the Breakdown Voltages of Kilo-Voltage Thin Film Transistors

Layered 2H-molybdenum ditelluride (MoTe2) is a promising near-infrared material with optical activity, which enables hybrid-integrated with silicon photonics for communication purposes. The use of various artificial hetero-stacking or twist-stacking techniques can further expand the emission bandwidth and offer more choices of optical-active materials used as building blocks in on-chip optoelectronic devices. However, while the twisting technique is an effective tool for adjusting interlayer interaction in van der Waals materials, a systematic experimental study of twisted MoTe2 homobilayers is currently lacking. Here, a series of MoTe2 homobilayers were prepared with precisely controlled twist-angles from 0° to 60°, with a particular focus on the small-twist region. Conducting photoluminescence measurements at low temperatures enabled observation of the evolution of exciton emission as the twist angle increases. Neutral and charged excitons were also identified in a dual-gated 1.4° twisted MoTe2 through gate-dependent and field-dependent photoluminescence measurements. Furthermore, spatially-resolved photoluminescence measurements revealed the critical role of the interface conditions, including interlayer spacing and strain, in addition to the twist-angle, in determining the excitonic behavior of the material. This study provides compelling experimental evidence for understanding the twist-angle-dependent excitonic behaviors in atomically thin semiconductors. 

H. Ou

Papers

Dual-material gate (DMG) field effect transistor

Critical Assessment of the High Carrier Mobility of Bilayer In2O3/IGZO Transistors and the Underlying Mechanisms

A multimode photodetector with polarization-dependent near-infrared responsivity using the tunable split-dual gates control

Widely Adjusting the Breakdown Voltages of Kilo-Voltage Thin Film Transistors

Exciton Emission in Molybdenum Telluride Homobilayers with Fine‐Tuned Twist‐Angles