In recent years, a large number of works have surfaced demonstrating applications of machine learning in the field of integrated circuit testing. Many of these works showcase the effectiveness of machine learning compared to the current industry practice on actual case studies with industrial data. The aim of the paper is to offer a concise and comprehensive tutorial on machine learning applications in integrated circuit testing and to provide some practical recommendations for practitioners.

Machine learning applications in IC testing

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.

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SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds

Multilevel data storage using resistive random access memory (RRAM) has attracted significant attention for addressing the challenges associated with the rapid advances in information technologies. However, it is still difficult to secure reliable multilevel resistive switching of RRAM due to the stochastic and multiple formation of conductive filaments (CFs). Herein, we demonstrate that a single CF, derived from selective oxidation by a structured Cu active electrode, can solve the reliability issue. High-quality pyramidal Cu electrodes with a sharp tip are prepared via the template-stripping method. Morphology-dependent surface energy facilitates the oxidation of Cu atoms at the tip rather than in other regions, and the tip-enhanced electric fields can accelerate the transport of the generated Cu ions. As a result, CF growth occurs mainly at the tip of the pyramidal electrode, which is confirmed by high-resolution electron microscopy and elemental analysis. The RRAM exhibits highly uniform and low formi...

Reliable Multistate Data Storage with Low Power Consumption by Selective Oxidation of Pyramid-Structured Resistive Memory.

This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

Making predictive analog/RF alternate test strategy independent of training set size

A calibration mechanism is often desired in analog/RF circuits that are designed in advance process nodes which exhibit large process variation, so as to recover yield loss and obtain the best possible trade-off between performances. In this paper, we present a calibration approach based on embedded sensors that has several appealing attributes. Specifically, it is virtually applicable to any circuit, the calibration mechanism is totally non-intrusive and, thereby, it does not degrade the performances of the circuit, and the calibration is performed in one-shot requiring a single test step, thus the calibration time is kept at a minimum. The proposed calibration approach is demonstrated experimentally on a 65 nm RF power amplifier based on fabricated chips from two corner wafers and a typical wafer.

One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits

In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.

Smart selection of indirect parameters for DC-based alternate RF IC testing

In this paper multilevel storage characteristic in Oxide-based Resistive RAM (OxRRAM) is demonstrated by modulating the amplitude of the cell programming voltages. Four resistance levels are clearly obtained. Impact of variability on a multilevel 1T-1R OxRRAM circuit is analyzed quantitatively at a circuit level to guarantee the robustness of the technology.

Multilevel operation in oxide based resistive RAM with SET voltage modulation

Specification testing, which involves the direct measurement of the circuit performance parameters is the conventional practice for testing analog/RF devices. While this approach is highly accurate, it often incurs extremely high testing costs. A promising approach is to adopt alternate test strategy, i.e. a strategy in which test results are derived from indirect low-cost measurements. The underlying idea is to learn during a training phase the mapping between indirect measurements and circuit performance parameters, and to use only indirect measurements to predict device specifications during production testing. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited, mainly because confidence in alternate test predictions is difficult to assess. In this paper, we propose a novel implementation with the objective to improve confidence in alternate test predictions. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions and remove these devices from the alternate test flow. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.

On the Use of Redundancy to Reduce Prediction Error in Alternate Analog/RF Test

This paper presents an optimized design of a high-speed digital IQ demodulator intended for the implementation of the feedback path of an adaptive base band pre-distorter (DPD). Indeed, the optimization of the DPD linearization capability in terms of correction bandwidth and nonlinearity effects minimization is directly related to the accuracy and speed of the IQ demodulator. In this work, a digital IQ demodulator is designed, optimized and implemented in a Xilinx FPGA device. This allowed a high speed processing of about 200MHZ with a substantial reduction of the FPGA used gates.

Haithem Ayari

Papers

Making predictive analog/RF alternate test strategy independent of training set size

Smart selection of indirect parameters for DC-based alternate RF IC testing

Multilevel operation in oxide based resistive RAM with SET voltage modulation

On the Use of Redundancy to Reduce Prediction Error in Alternate Analog/RF Test

Optimized Design of a Digital IQ Demodulator Suitable for Adaptive Predistortion of 3rd Generation Base Station PAs