A wideband noise-cancelling low-noise amplifier (LNA) combining resistor feedback and source-follower feedback (SFF) is proposed. The SFF facilitates upsizing of the feedback resistor to improve the gain and noise figure (NF), without compromising the input-impedance matching. Another benefit is that the noise contributions of both the feedback resistor and noise-cancelling transistors are significantly reduced. Fabricated in 65-nm CMOS, the LNA exhibits a voltage gain of 16.8 dB, and a flat NF of 3.3 ± 0.45 dB over a −3-dB bandwidth of 0.5 to 7 GHz. The power consumption is 11.3 mW at 1.2 V, and the die area is 0.044 mm2.

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A 0.044-mm 2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB

This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with a dual complementary pMOS–nMOS configuration to provide a current-reuse output. Triple-path noise-cancellation is effectively revealed to eliminate the thermal noise of the two CG transistors. Simultaneously, partial cancellation of intrinsic third-order distortion of output-stage transistors improves the input third-order intercept point (IIP3). In addition, we embed a resistive feedback in one of the auxiliary CS amplifiers to balance the multiple tradeoffs between noise figure (NF), input matching (S11), and forward gain (S21). Fabricated in 65-nm CMOS, the proposed wideband LNA exhibits an IIP3 of 2.2–6.8 dBm and an NF of 3.3–5.3 dB across a 19-GHz BW while consuming 20.3 mW at 1.6 V. S11 is $\pi $ -type input-matching network. The LNA exhibits a peak $\text{S}_{\vphantom {D_{j}}21}$ of 12.8 dB and occupies a very compact die area of 0.096 mm2.

A 0.096-mm $^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

LNAs for wideband receivers usually require a high linearity to protect the desired signals from out-band interference. Active feedback LNAs always suffer from the nonlinear feedback of source follower, and present a poor linearity. In order to solve this problem, a complementary source follower (CSF) is proposed, which utilizes the different characteristic of NMOS and PMOS to linearize the source follower, leading to an improvement of LNA’s IIP3 and IIP2 by about 10 dBm and 21 dBm respectively. In addition, a post-distortion technique is also used on the common source stage, which further enhances the IIP3 by about 2 dBm and IIP2 by 11 dBm. After using the two techniques, the noise figure (NF) does not deteriorate; instead it achieves a 0.3 dB improvement. A prototype is designed in TSMC 0.18 μm CMOS process, and a 14.8 mW power is dissipated from a 1.6 V supply. In typical process corner, across 0.3 to 3.5 GHz, this LNA achieves a 14.6 dB gain, a 2.9 dB minimum NF, and an IIP2 larger than +22 dBm and IIP3 larger than +1.2 dBm.

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

Pre-distortion technique to improve linearity of low noise amplifier

A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a $\pi$ -type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Multiple complementary nMOS and pMOS configurations commonly restrain nonlinear components in individual stage of the LNA. Complementary multigated transistor architecture is further employed to nullify the third-order distortion of noise-canceling stage and compensate the second-order nonlinearity of that. High third-order input intercept point (IIP3) is thus obtained, while the second-order input intercept point (IIP2) is guaranteed by differential operation. Implemented in a 0.18- $\mu \text{m}$ CMOS process, the experimental results show that the proposed LNA provides a maximum gain of 17.5 dB and an input 1-dB compression point (IP1 dB) of −3 dBm. An NF of 2.9–3.5 dB and an IIP3 of 10.6–14.3 dBm are obtained from 0.1 to 2 GHz, respectively. The circuit core only draws 9.7 mA from a 2.2 V supply.

A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

A wideband linearized common-gate low-noise amplifier (LNA) is proposed. The linearity is improved by active cross-coupled feedback technique. The active cross-coupled feedback circuit, consisting of a complementary source follower and a feedback capacitor, is employed to enhance loop gain, and acquire linearity improvement. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3). An enhanced LC-match input network and forward isolation of the active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance, respectively. Fabricated in a 0.13 μm RF CMOS process, the LNA achieves a flat voltage gain of 14.5 dB, an NF of 2.5---3.4 dB, and an IIP3 of 3.1---4.3 dBm over a 3 dB bandwidth of 0.1---1.2 GHz. It consumes only 3.5 mA from a 1.2 V supply and occupies an area of 0.2 mm2.

A linearized common-gate low-noise amplifier using active cross-coupled feedback technique

A complementary noise cancelling CMOS Low-noise amplifier (LNA) for mobile DTV application with enhanced linearity is proposed. Intrinsic noise cancellation mechanism maintains acceptable NF with reduced power consumption due to current reuse principle. Complementary multi-gated transistor (MGTR) technique is further employed to null the third-order distortion and compensate second-order nonlinearity of noise cancelling stage. Implemented in a 0.18-µm CMOS process, measurement results show that the proposed LNA provides a NF of 3 dB, and a maximum gain of 17.5 dB from 0.1 to 2 GHz. An input 1-dB compression point (IP1dB) and an IIP3 of −3 dBm and 14.3 dBm, respectively, are obtained. The circuit core only draws 9.7 mA from a 2.2 V supply.

A wideband complementary noise cancelling CMOS LNA

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies Implemented in a 018 μm CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 164 dB across the 3 dB bandwidth of 02–3 GHz The in-band noise figure of 34–47 dB is obtained while the IIP3 of 53–68 dBm and IIP2 of 125–172 dBm are post-simulated in the designed frequency band The LNA core consumes a power dissipation of 38 mW under a 15 V power supply

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

The invention discloses a linear broadband low noise amplifier. The linear broadband low noise amplifier is composed of two parts of symmetrical circuits, wherein the two parts of circuits comprise an input matching level, a common-gate level, an active feedback level and a load level; the amplifier is of a differential input/output structure; after a radio-frequency signal Vin+/- is inputted, then the radio-frequency signal is filtered by an input matching broadband and converted into a current signal by a common-gate transistor, then converted into an output signal Vout+/- at the load level after being amplified; a source follower and a feedback capacitor feed the output signal Vout+/- back to an input end of the common-gate transistor; the source follower adopts an NMOS (N-channel metal oxide semiconductor)/PMOS (P-channel Metal Oxide Semiconductor) complementary structure to acquire low second-order and third-order twist components, so as to reduce the nonlinear contribution to the low noise amplifier. The linear broadband low noise amplifier provided by the invention obviously improves the linearity of the amplifier within a wider frequency band, and maintains small noise figure and power consumption.

Haiyan Jin

Papers

A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

A linearized common-gate low-noise amplifier using active cross-coupled feedback technique

A wideband complementary noise cancelling CMOS LNA

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

Linear broadband low noise amplifier