Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way.

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The emergence of spin electronics in data storage

Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure The 4kbit spin-RAM was fabricated on a 4 level metal, 018 mum CMOS process In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

Towards spike-based machine intelligence with neuromorphic computing.

A method of manufacturing a nonvolatile memory device having a laminated structure in which a first magnetic material layer, a tunnel insulator film, and a second magnetic material layer are sequentially laminated, in which information is stored when an electric resistance value changes depending on a magnetization reversal state is disclosed. The method includes the steps of: sequentially forming the first magnetic material layer, the tunnel insulator film, and the second magnetic material layer; forming a mask layer on the second magnetic material layer; oxidizing a part uncovered by the mask layer of the second magnetic material layer; and reducing the oxidized part of the second magnetic material layer.

Method of manufacturing nonvolatile memory device

In this paper, we study to reduce the switching dispersion and improve 0/1 separation of Magnetic Tunnel Junction (MTJ) elements in order to realize high density MRAM. Various kinds of MTJ sizes and shapes have been evaluated and conclude that in ellipse like shape pattern aspect ratio more than 2 is enough for reproducing and reliable switching characteristics. As regards the reading characteristics, the combination of the optimized MTJ pattern and process makes 21.4 sigma separation between high and low resistance states. In further study of the relation between MTJ shapes and switching distribution, we found a "Saturn" shaped MTJ has best switching behavior. Also the toggle mode MRAM is evaluated and its effectiveness for high speed programming is confirmed.

A study for 0.18 /spl mu/m high-density MRAM

Disclosed is a nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other.

Nonvolatile magnetic memory device and photomask

The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.

Hajime Yamagishi

Papers

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

Method of manufacturing nonvolatile memory device

A study for 0.18 /spl mu/m high-density MRAM

Nonvolatile magnetic memory device and photomask

Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus