A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Fan-out semiconductor package

Synchronous Curable Deoxidizing Capability of Epoxy-Anhydride Adhesive: Deoxidation Quantification via Spectroscopic Analysis

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 $\mu \text{m}$ and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with ${S}$ -parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, $S_{11}$ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. ${S}$ -parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the ${S}$ -parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis

The electrification of the transportation sector is moving on at a fast pace. All car manufacturers have strong programs to electrify their car fleet to fulfill the demands of society and customers by offering carbon-neutral technologies to bring goods and persons from one location to another. Power electronics technology is, in this evolution, essential and also in a rapid development technology-wise. Some of the introduced technologies are quite mature, and the systems designed must have high reliability as they can be quite complicated from an electrical perspective. Therefore, this article focuses on the reliability of the used power electronic systems applied in electric vehicles (EVs) and hybrid EVs (HEVs). It introduces the reliability requirements and challenges given for the power electronics applied in EV/HEV applications. Then, the advances in power electronic components to address the reliability challenges are introduced as they individually contribute to the overall system reliability. The reliability-oriented design methodology is also discussed, including two examples: an EV onboard charger and the drive train inverter. Finally, an outlook in terms of research opportunities in power electronics reliability related to EV/HEVs is provided. It can be concluded that many topics are already well handled in terms of reliability, but issues related to complete new technology introduction are important to keep the focus on.

/pdf/reliability-of-power-electronic-systems-for-ev-hev-3jj2e48xde.pdf

Reliability of Power Electronic Systems for EV/HEV Applications

Catastrophic burn-out occurring during power-cycling of insulated gate bipolar transistor (IGBT) multichip modules has been observed to arise as a secondary failure mechanism caused by the lifting of the emitter aluminium bonding wires. In fact, the successive lift-off of the aluminium wires turns in a current crowding through few IGBT cells with consequent triggering of the internal parasitic thyristor-structure. Based on failure analysis data, this paper presents an exaustive description of the symptoms and a simple qualitative model for the time-dependent lift-off of aluminium bond wires in IGBT modules. This power-cycling induced failure mechanism (occurring in the field and during accelerated tests) is described in terms of plastic deformation of the aluminium interconnections (bond wires and chip-metallization) during pulsed operation. Some practical conclusions are finally drawn for power cycle testing and for optimal thermal design.

Plastic-strain of aluminium interconnections during pulsed operation of IGBT multichip modules

Power module packaging technologies have been experiencing extensive changes as the novel silicon carbide (SiC) power devices with superior performance become commercially available. This article presents an overview of power module packaging technologies in this transition, with an emphasis on the challenges that current standard packaging face, requirements that future power module packaging needs to fulfill, and recent advances on packaging technologies. The standard power module structure, which is a widely used current practice to package SiC devices, is reviewed, and the reasons why novel packaging technologies should be developed are described in this article. The packaging challenges associated with high-speed switching, thermal management, high-temperature operation, and high-voltage isolation are explained in detail. Recent advances on technologies, which try to address the limitations of standard packaging, both in packaging elements and package structure are summarized. The trend toward novel soft-switching power converters gave rise to problems regarding package designs of unconventional module configuration. Potential applications areas, such as aerospace applications, introduce low-temperature challenges to SiC packaging. Key issues in these emerging areas are highlighted.

A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues

For the fine-pitch application of flip-chip bonding with semiconductor packaging, fluxing and hybrid underfills were developed. A micro-encapsulated catalyst was adopted to control the chemical reaction at room and processing temperatures. From the experiments with a differential scanning calorimetry and viscometer, the chemical reaction and viscosity changes were quantitatively characterized, and the optimum type and amount of micro-encapsulated catalyst were determined to obtain the best pot life from a commercial viewpoint. It is expected that fluxing and hybrid underfills will be applied to fine-pitch flip-chip bonding processes and be highly reliable.

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.14.0113.0570

Characterization of Fluxing and Hybrid Underfills with Micro-encapsulated Catalyst for Long Pot Life

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-μm diameter and 60-μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.13.0213.0284

Fine-Pitch Solder on Pad Process for Microbump Interconnection

The rapid progress in silicon carbide (SiC)-based technology for high-power applications expects an increasing operation temperature (up to 250 °C) and awaits reliable packaging materials to unleash their full power. Epoxy-based encapsulant materials failed to provide satisfactory protection under such high temperatures due to the intrinsic weakness of epoxy resins, despite their unmatched good adhesion and processability. Herein, we report a series of copolymers made by melt blending novolac cyanate ester and tetramethylbiphenyl epoxy (NCE/EP) that have demonstrated much superior high-temperature stability over current epoxies. Benefited from the aromatic, rigid backbone and the highly functional nature of the monomers, the highest values achieved for the copolymers are as follows: glass-transition temperature (Tg) above 300 °C, decomposition onset above 400 °C, and char yield above 45% at 800 °C, which are among the highest of the known epoxy chemistry by far. Moreover, the high-temperature aging (250 °C) experiments showed much reduced mass loss of these copolymers compared to the traditional high-temperature epoxy and even the pure NCE in the long term by suppressing hydrolysis degradation mechanisms. The copolymer composition, i.e., NCE to EP ratio, has found to have profound impacts on the resin flowability, thermomechanical properties, moisture absorption, and dielectric properties, which are discussed in this paper with in-depth analysis on their structure-property relationships. The outstanding high-temperature stability, preferred and adjustable processability, and the dielectric properties of the reported NCE/EP copolymers will greatly stimulate further research to formulating robust epoxy molding compounds (EMCs) or underfill for packaging next-generation high-power electronics.

Melt Processable Novolac Cyanate Ester/Biphenyl Epoxy Copolymer Series with Ultrahigh Glass-Transition Temperature.

Popular solder-bumping mechanisms such as electroplating and stencil printing suffer from either high process costs or technical limitations. A low-cost solder-on-pad (SoP) process has been developed to meet the requirements of fine-pitch solder bumping. This paper focuses on the characterization and estimation of the SoP process. To form a solder bump without soldering defects, optimum process conditions should be carefully designed. A model to estimate the bump volume and predict the bump height is suggested. By optimizing the composition of solder paste material called solder-bump-maker, and by adjusting the process conditions, Sn-Ag-Cu solder bumps with different heights are obtained. The experiments and analysis to understand the impact of parameters were based on test vehicles with 80 μm pitch size. Then, the measured heights of solder bumps are compared with the model to see how they fit the estimation. Finally, a similar process has been conducted to test vehicles with pitch sizes of 150 and 40 μm, to confirm the scalability of the SoP process in different pitch sizes.

Haksun Lee

Papers

A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues

Characterization of Fluxing and Hybrid Underfills with Micro-encapsulated Catalyst for Long Pot Life

Fine-Pitch Solder on Pad Process for Microbump Interconnection

Melt Processable Novolac Cyanate Ester/Biphenyl Epoxy Copolymer Series with Ultrahigh Glass-Transition Temperature.

Characterization and Estimation of Solder-on-Pad Process for Fine-Pitch Applications