This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

Printed circuit board

A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

System and method for selective memory module power management

The application of adaptive power-supply regulation is extended to serial links The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution A prototype chip fabricated in 025-/spl mu/m CMOS process operates at 065-50 Gb/s while dissipating 97-380 mW

Adaptive supply serial links with sub-1-V operation and per-pin clock recovery

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Memory system topologies including a buffer device and an integrated circuit memory device

A high frequency bus system (450) which insures uniform arrival times of high fidelity signals to the devices (510), despite the use of the bus (450) on modules (420) and connectors. The high frequency bus system (450) includes a first bus segment having one or more devices (510) connected between a first and second end. The high frequency bus system (450) also includes a second bus segment which has no devices connected to it. The first end of the first segment and the second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device (510) connected to the first bus segment at substantially the same time. Conversely when two signals originate at a device (510) substantially at the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data, or control, carried by the signals.

High frequency bus system

A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Chip-to-chip communication system using an ac-coupled bus and devices employed in same

A 2 Gb/s/pin single-ended 4-PAM parallel bus interface uses transmit crosstalk cancellation and equalization techniques as well as integrating data receivers to improve system margin in low-cost packaging despite inherent coupling noise and data distortion.

A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-/spl mu/m CMOS and tested in a 28-/spl Omega/ evaluation system using on-chip 2/sup 10/ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices.

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A clock signal desired to be transmitted to various components of the electronic system is combined with a noise signal to generate a spread spectrum clock signal which, in turn, is distributed with an associated reference signal to selected components of the system using two-channel communication links. A receiving circuit within each of the selected components recovers the original clock signal from the spread spectrum clock signal and its associated reference signal. In one embodiment, the clock signal is combined with the noise signal in an exclusive-OR logic gate to generate a spread spectrum clock signal which is distributed to receiving components using a first channel. The noise signal is transmitted as the reference signal using the second channel. The two channel signals are combined in an exclusive-OR gate of one or more receiving circuits to recover the clock signal. In other embodiments, transmission of the clock signal is alternated between the two channels in accordance with the logic state of the noise signal. Here, the two channel signals are combined in an OR logic gate of each receiving circuit to recover the clock signal.

Haw-Jyh Liaw

Papers

High frequency bus system

Chip-to-chip communication system using an ac-coupled bus and devices employed in same

A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

Spread spectrum clocking of digital signals