H
Hideki Kitada
Researcher at Fujitsu
Publications - 107
Citations - 1119
Hideki Kitada is an academic researcher from Fujitsu. The author has contributed to research in topics: Wafer & Layer (electronics). The author has an hindex of 18, co-authored 107 publications receiving 1072 citations. Previous affiliations of Hideki Kitada include University of Tokyo & Tokyo Institute of Technology.
Papers
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Journal ArticleDOI
Thinned wafer multi-stack 3DI technology
Takayuki Ohba,Nobuhide Maeda,Hideki Kitada,Koji Fujimoto,Kousuke Suzuki,Tomoji Nakamura,Akihito Kawai,Kazuhisa Arai +7 more
TL;DR: In this article, the wafer-on-a-wafer (WOW) process is used for 3D stacking using wafers, and the vertical connection between TSV and Au is connected with a self-aligned contact without a bump electrode.
Proceedings ArticleDOI
Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory
Nobuhide Maeda,Y. S. Kim,Yukinobu Hikosaka,Takashi Eshita,Hideki Kitada,K. Fujimoto,Y. Mizushima,Kousuke Suzuki,Tomoji Nakamura,Akihito Kawai,Kazuhisa Arai,Takayuki Ohba +11 more
TL;DR: In this article, a 200mm and 300mm device wafers were successfully thinned down to less than 10-µm, and the switching charge showed no change in I on current nor junction leakage current.
Journal ArticleDOI
Advanced wafer thinning technology and feasibility test for 3D integration
Young Suk Kim,Nobuhide Maeda,Hideki Kitada,Koji Fujimoto,Shoichi Kodama,Akihito Kawai,Kazuhisa Arai,Kousuke Suzuki,Tomoji Nakamura,Takayuki Ohba +9 more
TL;DR: In this paper, an auto-TTV method was developed for the wafer-on-a-wafer (WOW) application, which measured wafer thickness and parallelity between grinder and wafer surface.
Patent
Semiconductor device with copper wiring and semiconductor device manufacturing method
TL;DR: In this article, an interlayer insulation film is deposited on a substrate in which a semiconductor element has been formed, and a wiring groove is formed in the interlayer insulating film.
Proceedings ArticleDOI
Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects
TL;DR: A non-Bosch etching process showed smooth sidewall surface and is considered to be feasible for reliable TSV interconnects, and FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking.