H
Hiroshi Yamaguchi
Researcher at NEC
Publications - 72
Citations - 490
Hiroshi Yamaguchi is an academic researcher from NEC. The author has contributed to research in topics: Signal & Lens (optics). The author has an hindex of 12, co-authored 72 publications receiving 490 citations. Previous affiliations of Hiroshi Yamaguchi include Panasonic.
Papers
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Patent
Organic electroluminescence element and image forming apparatus or portable terminal unit using thereof
Takafumi Hamano,Hisanori Sugiura,Naohide Wakita,Hiroshi Yamaguchi,Tomohiko Sasano,Yasuhiro Tanaka +5 more
TL;DR: In this article, the authors provided an organic electroluminescence element which is excellent in visibility and which can maintain a light emission performance with a high degree of efficiency, and an image forming apparatus which is good in visibility.
Patent
Edge input type backlight and liquid crystal display device
Kenichi Ikeda,Kenji Inoue,Takashi Kashiwabara,Shunsuke Kimura,Masayuki Takahashi,Hiroshi Yamaguchi,健二 井上,博史 山口,俊介 木村,隆司 柏原,健一 池田,昌之 高橋 +11 more
TL;DR: In this paper, a light emitting part formed by arranging a plurality of light emitting elements on an elongated board and sealing them by a transparent material was used to provide a backlight high in light utilization efficiency by suppressing generation of an illumination ineffective region in a light guide plate as much as possible.
Journal ArticleDOI
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems
Shunichi Kaeriyama,Yasushi Amamiya,Hidemi Noguchi,Z. Yamazaki,Tomoyuki Yamase,Kenichi Hosoya,M. Okamoto,S. Tomari,Hiroshi Yamaguchi,Hiroaki Shoda,H. Ikeda,Shinichi Tanaka,T. Takahashi,Risato Ohhira,A. Noda,Kenichiro Hijioka,Akira Tanabe,Sadao Fujita,Nobuhiro Kawahara +18 more
TL;DR: A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package that provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence.
Proceedings ArticleDOI
A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems
Yasushi Amamiya,Shunichi Kaeriyama,Hidemi Noguchi,Z. Yamazaki,Tomoyuki Yamase,K. Hosoya,M. Okamoto,S. Tomari,Hiroshi Yamaguchi,Hiroaki Shoda,H. Ikeda,Shinichi Tanaka,T. Takahashi,Risato Ohhira,A. Noda,K. Hijioka,Akira Tanabe,Sadao Fujita,Nobuhiro Kawahara +18 more
TL;DR: This paper presents 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology that consume 2.8W each and allow for a small and low-cost plastic BGA package.
Patent
Planar light source and liquid crystal display device
Hiroshi Yamaguchi,博史 山口 +1 more
TL;DR: In this article, a planar light source realizing a good color mix with compact and high light utilizing efficiency by using three primary color LEDs was provided. But the lighting means was provided with a plurality of linear light sources 3R, 3G, 3B having emission colors different from each other.