Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Nanoscale resistive switching devices, sometimes termed memristors, have recently generated significant interest for memory, logic and neuromorphic applications. Resistive switching effects in dielectric-based devices are normally assumed to be caused by conducting filament formation across the electrodes, but the nature of the filaments and their growth dynamics remain controversial. Here we report direct transmission electron microscopy imaging, and structural and compositional analysis of the nanoscale conducting filaments. Through systematic ex-situ and in-situ transmission electron microscopy studies on devices under different programming conditions, we found that the filament growth can be dominated by cation transport in the dielectric film. Unexpectedly, two different growth modes were observed for the first time in materials with different microstructures. Regardless of the growth direction, the narrowest region of the filament was found to be near the dielectric/inert-electrode interface in these devices, suggesting that this region deserves particular attention for continued device optimization.

/pdf/observation-of-conducting-filament-growth-in-nanoscale-sobo0w0qmm.pdf

Observation of conducting filament growth in nanoscale resistive memories

This review focuses on electrochemical metallization memory cells (ECM), highlighting their advantages as the next generation memories. In a brief introduction, the basic switching mechanism of ECM cells is described and the historical development is sketched. In a second part, the full spectra of materials and material combinations used for memory device prototypes and for dedicated studies are presented. In a third part, the specific thermodynamics and kinetics of nanosized electrochemical cells are described. The overlapping of the space charge layers is found to be most relevant for the cell properties at rest. The major factors determining the functionality of the ECM cells are the electrode reaction and the transport kinetics. Depending on electrode and/or electrolyte material electron transfer, electro-crystallization or slow diffusion under strong electric fields can be rate determining. In the fourth part, the major device characteristics of ECM cells are explained. Emphasis is placed on switching speed, forming and SET/RESET voltage, R(ON) to R(OFF) ratio, endurance and retention, and scaling potentials. In the last part, circuit design aspects of ECM arrays are discussed, including the pros and cons of active and passive arrays. In the case of passive arrays, the fundamental sneak path problem is described and as well as a possible solution by two anti-serial (complementary) interconnected resistive switches per cell. Furthermore, the prospects of ECM with regard to further scalability and the ability for multi-bit data storage are addressed.

https://iopscience.iop.org/article/10.1088/0957-4484/22/25/254003/pdf

Electrochemical metallization memories—fundamentals, applications, prospects

A reconfigurable LSI employing a nonvolatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid electrolyte copper sulfide, has a <30-nm contact diameter and <100-/spl Omega/ on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 /spl times/ 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18-/spl mu/m CMOS technology, and operational tests with them have confirmed the switch's potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated.

A nonvolatile programmable solid electrolyte nanometer switch

Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

Clock adjusting circuit and semiconductor integrated circuit device

A small-size on-chip transformer-based digital isolator for power control systems is proposed. With a proposed pulse generation and detection scheme that enables a 5 V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4-1/8 that of conventional transformers. A test chip achieves a 2.5 kV isolation voltage, a 35 kV/us CMR, a 1.6 mA static current and a 250 Mbps data rate, all which are equal to or superior to those of optocouplers or conventional digital isolators. The developed technology greatly reduces the number of chips in power control systems by allowing integration of multiple isolators in a CMOS chip together with microcontrollers or gate drivers. Moreover, the high-speed low-power capability expands the application potential to include isolated serial links, controller area network (CAN), FlexRay, medical devices, displays, sensors, etc.

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique

A backplane transceiver in 90 nm CMOS that employs duobinary signaling over copper traces is described. To introduce duobinary signaling into data transfers on printed boards, three techniques are developed: 1) edge equalization for equalizer adaptation; 2) 2/spl times/ oversampled transmitter equalizer for ISI control; and 3) 2b-transition-ensure encoding for clock recovery.

12Gb/s duobinary signaling with /spl times/2 oversampled edge equalization

We have developed a solid-electrolyte nonvolatile switch (here we refer as NanoBridge) with a low ON resistance and its small size. When we use a NanoBridge to switch elements in a programmable logic device, the chip size (or die cost) can be reduced and performance (speed and power consumption) can be enhanced. Developing this application required solving a couple of problems. First, the switching voltage of the NanoBridge (∼ 0.3 V) needed to be larger than the operating voltage of the logic circuit (> 1 V). Second, the programming current (> 1 mA) needed to be suppressed to avoid large power consumption. We demonstrate how the Nanobridge enhances the switching voltage and reduces the programming current.

Shunichi Kaeriyama

Papers

A nonvolatile programmable solid electrolyte nanometer switch

Clock adjusting circuit and semiconductor integrated circuit device

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique

12Gb/s duobinary signaling with /spl times/2 oversampled edge equalization

Solid-electrolyte nanometer switch