Showing papers by "Hiroshi Yoshida published in 2007"

Cognitive radio system

Abstract: A cognitive radio system includes: a state detecting device that scans a frequency band allocated to another radio system than the cognitive radio system to detect a first use-state of the frequency band; a first server including a first gathering unit that receives first information relating to the first use-state and a second gathering unit; a second server that stores a second use-state of the frequency band allocated to the other radio system, the second server configured to provide second information relating to the second use-state to the second gathering unit; and a notifying unit that notifies a terminal device in the cognitive radio system of information of an available channel based on the first information and the second information.

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller

Abstract: In direct conversion receivers, which down-convert RF signal to baseband directly, DC offset in the baseband signal significantly degrades receiver performance and thus the DC offset cancellation is one of the most important issues regarding the achievement of high receiving performance. This paper proposes a fast-settling DC offset canceller that eliminates DC offset using stored DC data estimated in advance so as to cancel residual DC offset by a feedback loop. Experimental results and computer simulation results show that the DC offset canceller can eliminate a DC offset within 5 [musec], although it does not remove the desired signal component so as not to degrade BER (bit error rate) performance, because cut-off frequency in the HPF (high-pass filter) characteristic due to DC offset cancellation can remain low.

Second-order ΔΣAD modulator with novel feedforward architecture

Abstract: This paper proposes novel feedforward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology. DeltaSigmaAD modulator realizes high resolution by oversampling and noise shaping technique. However, its SNDR (signal to noise and distortion ratio) is limited by the dynamic range of the input signal and non-idealities of building blocks, particularly by the harmonic distortion in amplifier circuits. Compared with a feed backed DeltaSigmaAD modulator, in a full feedforward DeltaSigmaAD modulator structure, the signal transfer function is unity under ideal circumstances. It means that the signal swings through the loop filter become smaller. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirement for amplifiers in low-voltage design. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before quantizer. Especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to large chip area and extra power dissipation. In this paper, we propose a novel architecture of a feedforward DeltaSigmaAD modulator. It realizes the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low-power dissipation. We also conducted MATLAB and SPICE simulations to verify the proposed architecture and modulator circuits.

Receiver, wireless device and method for cancelling a DC offset component

Abstract: A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.

Transmitting apparatus and method, receiving apparatus and method

Abstract: A transmitting apparatus converts a unit data item of the unit data items having a predetermined bit length into a time shift amount, stores, in a memory, a first symbol including a plurality of samples, generates a second symbol corresponding to the unit data item by cyclically shifting the samples in the first symbol by the time shift amount, and transmits the second symbol. A receiving apparatus receives two consecutive symbols each including a plurality of samples, detects sample values of the samples in each of the symbols, detects a time shift amount between the symbols based on the sample values of the samples in each of the symbols, and converts the time shift amount into a data item having the bit length.

Wireless receiver and wireless receiving method

Abstract: PROBLEM TO BE SOLVED: To attain lower power consumption when receiving wireless packets containing MIMO signal. SOLUTION: The wireless receiver comprises n pieces (n is integer of 2 or more) of receiving branches (antennas 101A-101C, receivers 102A-102C, and A/D converters 103A-103C) that can receive wireless packets containing first signal (L-STF, L-LTF, and L-SIG) of single stream, second signal (HT-SIG1, and HT-SIG2) that shows transmission of a third signal containing data of a plurality of streams, and third signal (HT-STF, HT-LTF1, HT-LTF2, and DATA). It also comprises units (104, 103-111) which demodulate and decode the output signal of the receiving branch; and a power control unit 105 which controls supplying of power to m pieces (m is integer of m COPYRIGHT: (C)2007,JPO&INPIT

An HPSK/OFDM 64-QAM dual-mode doherty power amplifier module for mobile terminals

Abstract: This paper presents a miniaturized dual-mode Doherty PA module applicable for an HPSK signal and an OFDM 64-QAM signal. Dual-mode operation with identical hardware is realized by introducing a bias switching technique, which changes bias conditions of amplifiers according to transmission signals, and employing dual-mode matching circuits, which are designed based on the results of load-pull measurements using an HPSK signal and an OFDM 64-QAM signal. The Doherty PA module consists of a Doherty stage and a gain stage. Two GaAs-HBTs for a Doherty stage and one GaAs-HBT for a gain stage are integrated onto a 1 mm-square single GaAs-MMIC. In the HPSK mode, maximum output power of 26.7 dBm, power added efficiency (PAE) of 41%, and power gain of 27 dB are obtained in the condition that adjacent channel leakage power ratio (ACLR) is under -38 dBc. In the OFDM 64-QAM mode, maximum output power of 21.0dBm, PAE of 27%, and power gain of 28 dB are obtained under EVM < 3.0%. This is the first multi-mode Doherty PA module suitable for multi peak to average power ratio (PAPR) signals.

A 0.13/spl mu/m CMOS 5GHz Fully Integrated 2x3 MIMO Transceiver IC with over 40dB Isolation

Abstract: A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain amplifier is proposed for low power operation. Isolation of over 40 dB is obtained by equipping separate GNDs on both the MIMO IC and the circuit board. This results in negligible degradation of EVM. TX EVM of over -31 dB is obtained at -8.6 dBm for 2 TX mode when external LO of 10 GHz is applied. The 3 RXs and 2 TXs with LO paths dissipate 703 mW and 412 mW from 1.5 V, respectively.

Receiving device, radio device, and offset canceling method

Abstract: PROBLEM TO BE SOLVED: To effectively remove DC offset components even when a reception signal has an amplification gain. SOLUTION: A receiving device has a storage unit which stores a DC offset amount remaining in the reception signal, a first DC offset removing unit which generates a first DC offset amount on the basis of the DC offset amount stored in the storage unit and removes the first DC offset amount from the reception signal, an amplifier which amplifies the signal output from the first DC offset removing unit, and a DC offset removing unit which generates a second DC offset amount on the basis of the DC offset amount stored in the storage unit and the amplification factor of the amplifier, and removes the second DC offset amount from the signal amplified by the amplifier. COPYRIGHT: (C)2008,JPO&INPIT