Low-Frequency Noise in Advanced CMOS Devices begins with an introduction to noise, describing the fundamental noise sources and basic circuit analysis. The characterization of low-frequency noise is discussed in detail and useful practical advice is given. The various theoretical and compact low-frequency (1/f) noise models in MOS transistors are treated extensively providing an in-depth understanding of the low-frequency noise mechanisms and the potential sources of the noise in MOS transistors. Advanced CMOS technology including nanometer scaled devices, strained Si, SiGe, SOI, high-k gate dielectrics, multiple gates and metal gates are discussed from a low-frequency noise point of view. Some of the most recent publications and conference presentations are included in order to give the very latest view on the topics. The book ends with an introduction to noise in analog/RF circuits and describes how the low-frequency noise can affect these circuits.

Low-Frequency Noise in Advanced MOS Devices

We describe an implementation of the density-gradient device equations which is simple and works in any dimension without imposing additional requirements on the mesh compared to classical simulations. It is therefore applicable to real-world device simulation with complex geometries. We use our implementation to determine the quantum mechanical effects for a MOS-diode, a MOSFET and a double-gated SOI MOSFET. The results are compared to those obtained by a 1D-Schrodinger-Poisson solver. We also investigate a simplified variant of the density-gradient term and show that, while it can reproduce terminal characteristics, it does not give the correct density distribution inside the device.

Quantum device-simulation with the density-gradient model on unstructured grids

In this paper, we present a comprehensive experimental characterization of electron and hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n- and p-MOSFETs. Measurements have been performed at different temperatures using a special test structure able to circumvent parasitic resistance effects. Our results indicate that, at large inversion densities (N/sub inv/), the mobility of ultrathin SOI transistors is largely insensitive to silicon thickness (T/sub SI/) and is larger than in heavily doped bulk MOS because of a lower effective field. At small N/sub inv/, instead, mobility of SOI transistors exhibits a systematic reduction with decreasing T/sub SI/. The possible explanation for this /spl mu//sub eff/ degradation in extremely thin silicon layers is discussed by means of a comparison to previously published experimental data and theoretical calculations. Our analysis suggests a significant role is played by an enhancement of phonon scattering due to carrier confinement in the thinnest semiconductor films. The experimental mobility data have then been used to study the possible implications for ultrashort SOI transistor performance using numerical simulations.

Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (?V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ?V th and is therefore proportional to the trend of ?V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

/pdf/process-variation-effect-metal-gate-work-function-4imcvux98y.pdf

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing ldquodopant concentration variationrdquo and ldquodopant position fluctuation.rdquo As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.

https://ir.nctu.edu.tw:443/bitstream/11536/8754/1/000256155600023.pdf

Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS

A new, comprehensive, physically-based, semiempirical, local model for transverse-field dependent electron and hole mobility in MOS transistors is presented. In order to accurately predict the measured relationship between the effective mobility and effective electric field over a wide range of substrate doping and bias, we account for the dependence of surface roughness limited mobility on the inversion charge density, in addition to including the effect of coulomb screening of impurities by charge carriers in the bulk mobility term. The result is a single mobility model applicable throughout a generalized device structure that gives good agreement with measured mobility data and measured MOS I-V characteristics over a wide range of substrate doping, channel length, transverse electric field, substrate bias, and temperature.

Hong Ha Vuong

Papers

An improved electron and hole mobility model for general purpose device simulation