H
Howard H. Chen
Researcher at IBM
Publications - 42
Citations - 941
Howard H. Chen is an academic researcher from IBM. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 15, co-authored 42 publications receiving 935 citations.
Papers
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Proceedings ArticleDOI
Power supply noise analysis methodology for deep-submicron VLSI chip design
Howard H. Chen,David D. Ling +1 more
TL;DR: A new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block offers the most complete and accurate analysis of Vdd distribution.
Patent
Apparatuses for Dissipating Heat from Semiconductor Devices
TL;DR: In this article, an apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having base section, and a plurality of three-dimensional (3D) shaped members.
Patent
Cooling system for a semiconductor device and method of fabricating same
TL;DR: In this article, a cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the substrate, and thermally conductive material deposited in the plurality of trench patterns.
Patent
Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate
TL;DR: A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region as mentioned in this paper, which includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.
Patent
Sea-of-fins structure on a semiconductor substrate and method of fabrication
TL;DR: In this paper, a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation, forming a nitride spacer around each of the plurality of fin bodies, forming an isolation region in between each fin body, and coating the plurality, the nitride spacers, and the isolation regions with a protective film.