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Design Of Analog Cmos Integrated Circuits

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

A gesture recognition method includes detecting multiple pointers in close proximity to a touch surface to determine if the multiple pointers are being used to perform a known gesture. When the multiple pointers are being used to perform a known gesture, executing a command associated with the gesture. A touch system incorporating the gesture recognition method is also provided.

Gesture recognition method and touch system incorporating the same

A passive touch system includes a passive touch surface and at least two cameras associated with the touch surface. The at least two cameras acquire images of the touch surface from different locations and have overlapping fields of view. A processor receives and processes images acquired by the at least two cameras to detect the existence of a pointer therein and to determine the location of the pointer relative to the touch surface. Actual pointer contact with the touch surface and pointer hover above the touch surface can be determined.

Passive touch system and method of detecting user input

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications by using an energy-efficient ADC. A successive-approximation register (SAR) architecture, mostly composed of digital circuits, can achieve low power under low supply voltages [1,2]. Power consumption can be decreased by using either an energy-efficient capacitive-DAC switching method [1] or a low-power comparator with a majority voting technique [2]. In this work, a small coarse ADC resolves the MSB bits. Then, a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy. The comparator power is also decreased by utilizing a low-power comparator during coarse conversion and a low-noise comparator during fine conversion. As a result, its FoM performance is as low as 0.85fJ/conversion-step, which is about 3 times better than that of the state-of-the-art work [2].

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.

A 14-b 20-Msamples/s CMOS pipelined ADC

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy

Calibration of resistor ladder using difference measurement and parallel resistive correction

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs.

A High-Efficiency CMOS DC-DC Converter With 9- $\ \mu$ s Transient Recovery Time

A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

Hsin-Shu Chen

Papers

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

A 14-b 20-Msamples/s CMOS pipelined ADC

Calibration of resistor ladder using difference measurement and parallel resistive correction

A High-Efficiency CMOS DC-DC Converter With 9- $\ \mu$ s Transient Recovery Time

Analog to digital converter using subranging and interpolation