A 14-b 20-Msamples/s CMOS pipelined ADC

TLDR: Capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors.

Abstract: The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.