Recent technological demand of FinFETs have been explored and reviewed in this work. The downscaling of the conventional MOSFET urge to the researchers to innovate new electronic switches with improved performance in low power parameters and reduced short channel effects (SCE). Control of gate over the channel charge could be increased by using FinFET based multi-gate technology. In this review paper, we have studied about the parasitic capacitances and low power FinFET applications. The challenges of the FinFET technologies have also addressed to explore the research discontinuity.

Recent trend of FinFET devices and its challenges: A review

A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel protrudes from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

Vertical channel memory and manufacturing method thereof and operating method using the same

A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Vertical channel transistor structure and manufacturing method thereof

A new body-on-insulator (BOI) FinFET device structure based on bulk-Si substrate has been proposed and experimentally demonstrated in this paper. In comparison with other bulk FinFETs, the BOI FinFET features the localized insulator below the Si-Fin body, which can achieve both low source/drain (S/D) parasitic resistance and effective suppression of the S/D leakage beneath the Si-Fin channel, as well as good heat dissipation capability. The device fabrication process is basically compatible with conventional CMOS technology. High drive current, low subthreshold swing, and excellent short-channel behavior are observed in the fabricated BOI FinFETs.

High-Performance BOI FinFETs Based on Bulk-Silicon Substrate

A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash

A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand -Type Flash Memory

High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time A program/erase window of 2V has been achieved with high P/E speed (TP equiv 10mus and TE equiv 1ms), and a 15V window remained after 10 years at room temperature Multi-level storage is also obtained with DeltaVt > 4V and TP,E equiv 1 ms Operation voltages are not more than 7V in the two applications Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines

Huan-Chi Ma

Papers

20nm gate bulk-finFET SONOS flash

Time-dependent behaviour of circular steel tube confined reinforced concrete (STCRC) slender columns