J
Jyu-Horng Shieh
Researcher at TSMC
Publications - 76
Citations - 1069
Jyu-Horng Shieh is an academic researcher from TSMC. The author has contributed to research in topics: Layer (electronics) & Substrate (printing). The author has an hindex of 16, co-authored 76 publications receiving 1055 citations.
Papers
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Proceedings ArticleDOI
5nm-gate nanowire FinFET
Fu-Liang Yang,Di-Hong Lee,Hou-Yu Chen,Chang-Yun Chang,Sheng-Da Liu,Cheng-Chuan Huang,Tang-Xuan Chung,Hung-Wei Chen,Chien-Chao Huang,Yi-Hsuan Liu,C.C. Wu,Chi-Chun Chen,Shih-Chang Chen,Ying-Tsung Chen,Ying-Ho Chen,C.H. Chen,Bor-Wen Chan,Peng-Fu Hsu,Jyu-Horng Shieh,Han-Jan Tao,Yee-Chia Yeo,Yiming Li,Jam-Wem Lee,Pu Chen,Mong-Song Liang,Chenming Hu +25 more
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Patent
Multi-patterning method and device formed by the method
Chia-Ying Lee,Jyu-Horng Shieh +1 more
TL;DR: In this paper, a multi-patterning method is proposed, where each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask.
Patent
Spacer Etching Process For Integrated Circuit Design
Ru-Gun Liu,Cheng-Hsiung Tsai,Chung-Ju Lee,Lai Chih-Ming,Chia-Ying Lee,Jyu-Horng Shieh,Ken-Hsien Hsieh,Ming-Feng Shieh,Shau-Lin Shue,Shih-Ming Chang,Tien-I Bao,Tsai-Sheng Gau +11 more
TL;DR: In this article, a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the material layer is presented.
Proceedings ArticleDOI
20nm gate bulk-finFET SONOS flash
Jiunn-Ren Hwang,Tsung-Lin Lee,Huan-Chi Ma,Tzyh-Cheang Lee,Tang-Hsuan Chung,Chang-Yun Chang,Sheng-Da Liu,Baw-Ching Perng,Ju-Wang Hsu,Ming-Yong Lee,Chih-Yuan Ting,Chien-Chao Huang,Ji-Hua Wang,Jyu-Horng Shieh,Fu-Liang Yang +14 more
TL;DR: In this paper, high performance FinFET SONOS flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time.
Patent
Method for preventing photoresist poisoning
TL;DR: In this paper, a method for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer was provided.