A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Standard cell layout, semiconductor device having engineering change order (eco) cells and method

PROBLEM TO BE SOLVED: To reduce, in a semiconductor integrated circuit device including a standard cell with a fin transistor, an influence of a cell arrangement on the characteristics of the fin transistor.SOLUTION: A standard cell 1 constituting a semiconductor integrated circuit device includes a plurality of fins 11, 12, 13 and 14 extending in a first direction and arranged in a second direction that is perpendicular to the first direction. Active fins 11 and 12 form active transistors. Dummy fins 13 and 14 are disposed between the active fin 11 and an end of the standard cell 1 and between the active fin 12 and the other end of the standard cell 1, respectively.SELECTED DRAWING: Figure 1

Semiconductor integrated circuit device

Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

Methods of generating integrated circuit layout using standard cell library

A radio frequency (RF) switch includes a heating element, a nugget, a phase-change material (PCM), and input/output contacts. The nugget comprises thermally conductive and electrically insulating material, and is situated on top of the heating element. The PCM has an active segment approximately situated over the nugget, and passive segments approximately situated under the input/output contacts. The PCM RF switch may include thermally resistive material adjacent to first and second sides of the heating element, and/or adjacent to first and second sides of the nugget. The PCM RF switch may include a heat valve under the heating element.

High reliability RF switch based on phase-change material

A semiconductor device includes a plurality of vertical-transport fin field effect transistors that are arranged at a locally-variable fin pitch. Within a first region of the device, a first plurality of fins are arranged at a first pitch (d 1 ), and within a second region of the device, a second plurality of fins are arranged as a second pitch (d 2 ) less than the first pitch. The second plurality of fins share merged source, drain and gate regions, while the source, drain and gate regions for the first plurality of fins are unmerged.

Vertical-transport FinFET device with variable Fin pitch

A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.

System and method of layout design for integrated circuits

A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Method of Forming Layout Design

A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.

Standard cell metal structure directly over polysilicon structure

A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

Hui-Zhong Zhuang

Papers

Standard cell layout, semiconductor device having engineering change order (eco) cells and method

System and method of layout design for integrated circuits

Method of Forming Layout Design

Standard cell metal structure directly over polysilicon structure

Method and system of forming layout design