L
Lin Chung-Te
Researcher at TSMC
Publications - 19
Citations - 49
Lin Chung-Te is an academic researcher from TSMC. The author has contributed to research in topics: Integrated circuit layout & Layer (electronics). The author has an hindex of 5, co-authored 19 publications receiving 49 citations.
Papers
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Patent
Method of Forming Layout Design
Tung-Heng Hsieh,Lin Chung-Te,Sheng-Hsiung Wang,Hui-Zhong Zhuang,Min-Hsiung Chiang,Chiang Ting-Wei,Li-Chun Tien +6 more
TL;DR: In this article, a method of forming a layout design for fabricating an integrated circuit (IC) is disclosed, which includes identifying one or more areas in the layout design occupied by one or many segments of a plurality of gate structure layout patterns.
Patent
Semiconductor device and method of manufacturing semiconductor device
Tung-Heng Hsieh,Zhuang Hui-Zhong,Lin Chung-Te,Ting-Wei Chiang,Sheng-Hsiung Wang,Li-Chun Tien +5 more
TL;DR: In this article, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with the top surfaces of the second conductive features.
Patent
System and method of processing cutting layout and example switching circuit
Tung-Heng Hsieh,Zhuang Hui-Zhong,Lin Chung-Te,Sheng-Hsiung Wang,Chiang Ting-Wei,Li-Chun Tien +5 more
TL;DR: In this paper, a method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed, which includes determining if a first CUT layout pattern and a second CUT pattern are in compliance with a predetermined spatial resolution requirement.
Patent
Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device
Tung-Heng Hsieh,Hui-Zhong Zhuang,Lin Chung-Te,Sheng-Hsiung Wang,Chiang Ting-Wei,Li-Chun Tien,Tsung-Chieh Tsai +6 more
TL;DR: In this paper, a semiconductor device includes a substrate having an active area, a gate structure over the active area and an upper conductive layer over and electrically coupled to the lower conductive layers.
Patent
Integrated circuit with elongated coupling
Tung-Heng Hsieh,Hui-Zhong Zhuang,Lin Chung-Te,Chiang Ting-Wei,Sheng-Hsiung Wang,Li-Chun Tien +5 more
TL;DR: In this paper, a first layer comprises a set of first lines and a second layer consists of second lines, each of which has a pitch measured between the lines of the first lines in the first direction.