Impact life prediction modeling of TFBGA packages under board level drop test

Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Drop impact reliability testing for lead-free and lead-based soldered IC packages

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

A solder ball shear and pull testing study was conducted on 27 unique package constructions, evaluated under a wide variety of test conditions. The study encompassed the coordinated efforts of 7 electronics manufacturers using early-prototype high speed solder ball shear/pull equipment. Shear speeds ranged from a conventional 0.0001 m/s (100 /spl mu/m/s) rate up to as high as 4 m/s, while pull testing ranged from speeds of 0.0005 m/s (500 /spl mu/m/s) to 1.3 m/s. The many package configurations varied in substrate plating type (exposed Cu, electrolytic NiAu and electroless-Ni/immersion-Au), solder composition (SnPb, SnPbAg and SnAgCu), packaging construction and materials, solder and package geometries, package assembly location, and time between reflow and test.

BGA brittle fracture - alternative solder joint integrity test methods

Reliabilit!- perfonnance of IC packages during drop impact is critical, especially for handheld electronic products. Currently. thcrc is no detailed test standard in the industry to advise on the procedures for board level dmp test. nor there is any model Ilia1 providcs good correlation with experimental ineasiircinents of acceleration and impact life. In this paper; detailed drop tests and simulations are pcrfonned on TFBGA (Thin-profile Fine-pitch BGA) and VFBGA (Vey-thinprofile Fine-pitch BGA) packages at board level using testing procediires developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and iueclwnical shock during impact. The critical solder ball is obsewed to occur at the outennost comer solder .joint_ and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically. to understand the effects of drop heightl drop oricntation, number of PCB mounting screws to fixture. position of component on board: PCB bending: solder material, and etc. Drop height, fclt thickness, and contact conditions are used to fine-tune the shape aud level of shock pulse required. Board level drop test can be better controlled. compared with system or product level test such as impact of mobile phone. which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At tlie same time, dynamic simulation is perfonncd to compare with esperiniental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estiinatc the number of drops to failure for a package. For the correlation cases studied. the nminmm nonual peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within M drops, for a typical test of 50 drops. With this new model, a failure-free state can be detennined, and drop test performance of new package design can be quantified. and fuliher enhanced through modeling. This quantitative approach is different from traditional qualitative modeling. as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test ,and thennal cycling test. Different design guidelines should be considered, depcnding on application and area of concern

Board level drop test and simulation of TFBGA packages for telecommunication applications

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

Due to demand for short time-to-market, drop testing has become a bottleneck for semiconductor and telecommunication industry. Therefore, there is a need for a faster and cheaper solution, i.e. validated drop impact model, which is accurate, reliable, and enables understanding of physics-of-failure for design improvement. Currently, there has been increasing interest and effort by researchers on board level drop test studies by numerical modeling. Several different modeling methods have been developed to satisfy the requirements in package design analysis, product qualification, and impact life prediction. In this paper, for the first time, various advanced drop test modeling techniques developed are systematically introduced, integrated, compared, and recommended for various applications, consisting of analysis type (dynamic vs. static), loading method (free-fall vs. input-G), and solver algorithm (explicit vs. implicit). Each combination of modeling techniques has its unique advantages, depending on applications. All the models are validated to show excellent first level correlation on the dynamic responses of PCB, second level correlation on the solder joint stress and failure mode, and third level correlation on impact life prediction. Dynamic model is required for accurate drop impact simulation, whereas static model is useful for quick design analysis and optimization. The free-fall drop model can be applied to provide fundamental understanding of different drop test conditions, i.e. drop height, contact surface, drop block, felt layer on the impact pulse. Once the impact pulse has been established, the input-G method can be used as a standard "numerical drop test" to perform design analysis and optimization for product qualification. Implicit solver is an alternative to explicit solver, saving software cost by maintaining only one type of solver, but the technical challenge is greater.

http://ieeexplore.ieee.org/iel5/9844/31024/01441312.pdf

Hun Shen Ng

Papers

Impact life prediction modeling of TFBGA packages under board level drop test

Board level drop test and simulation of TFBGA packages for telecommunication applications

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

Development and application of innovational drop impact modeling techniques