An overview of through-silicon-via technology and manufacturing challenges

A stacked-die product integrates multiple dies on interposers. In this paper, we first discuss the difficulties of traditional testing mechanism for interposers. To improve production yield, a contactless testing mechanism for pre-bond interposers is proposed. Our testing mechanism attempts to detect a defective interposer from the thermal image after heating the interposer. We propose to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective. Experimental results show that our testing mechanism can efficiently improve the yield from 70.5% to 96.84%.

Contactless Stacked-die Testing for Pre-bond Interposers

This paper introduces a manufacturing process screening methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve "More than Moore's law" for mobile devices – more so than 3D integrated circuits (3DIC). InFO WLCSP has several test challenges due to new defect modes that have never been faced before. Previous test methods take long test time and often have poor test performance. In this paper we propose test solutions that lead to a short test time and a higher test coverage for yield learning. We will demonstrate the methodology in some industrial cases to validate our claims.

http://ieeexplore.ieee.org/iel7/7602792/7604713/07604720.pdf

Novel info wafer-level-chip-scale-package N-leak test and stress

In this paper, we study the testing flow in fabrication process of stacked-die products. We discuss the difficulties of traditional testing mechanism. To improve production yield, a contactless testing with cyber physical system (CPS) for pre-bond interposers is proposed in this paper. We propose a testing framework comprising a heating laser and an infrared-radiation camera. In addition, we also build a completely correct model of a functional interposer. By our proposed Classification Algorithm and BDA classifier, functional and defective interposers can be differentiated. Our experimental results show that the proposed framework provides an over 97% accuracy to identify functional interposers from a whole batch of untested products.

Cyber physical system (CPS) for contactless IC testing

Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.

Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology

A novel test module (NTM) for daisy chain test is proposed. In the daisy chain test, the defected chains and components can be easily observed and repaired rapidly by the proposed technology. Besides, the cost of proposed module is much cheaper than the price of tester improvement. Finally, the measured results of the test with NTM are also proposed for verification. The proposed module can save not only debugging time but also the cost in the daisy chain test.

Hung-Chih Lin

Papers

Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology

A novel test module for interconnect diagnosis enhancement and quality improvement in daisy chain test