An overview of through-silicon-via technology and manufacturing challenges

A system and method for evaluating wafer test probe cards under real-world wafer test cell condition integrates wafer test cell components into the probe card inspection and analysis process. Disclosed embodiments may utilize existing and/or modified wafer test cell components such as, a head plate, a test head, a signal delivery system, and a manipulator to emulate wafer test cell dynamics during the probe card inspection and analysis process.

Probe card analysis system and method

A stacked-die product integrates multiple dies on interposers. In this paper, we first discuss the difficulties of traditional testing mechanism for interposers. To improve production yield, a contactless testing mechanism for pre-bond interposers is proposed. Our testing mechanism attempts to detect a defective interposer from the thermal image after heating the interposer. We propose to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective. Experimental results show that our testing mechanism can efficiently improve the yield from 70.5% to 96.84%.

Contactless Stacked-die Testing for Pre-bond Interposers

The invention discloses a method for an array microprobe full-automatic test of a packaged wafer. The method comprises steps: using machine vision to obtain a wafer partial position image, calculating the precise position of the wafer through an image processing algorithm; realizing accurate alignment of a microprobe array with micro-convex points on a chip, and making the microprobe array contact with the micro-convex points; leading out electrical properties of the chip through the microprobes, analyzing and determining the electrical properties, so as to complete the test of the chip. The invention also discloses a system for an array microprobe full-automatic test of a packaged wafer. The system comprises a motion platform, a wafer supporting table, a vision module, a motion control card, a probe card module, a four-wire type wire rod test machine, and a computer. The wafer supporting table, the vision module, and the probe card module are installed on the motion platform, and move with the motion platform. The motion control card controls movement of the motion platform. The probe card module is connected with the four-wire type wire rod test machine. The computer is connected with the motion control card and the four-wire type wire rod test machine.

System and method for array microprobe full-automatic test of packaged wafer

A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.

Wafer-level gate stress testing

A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies.

Method and apparatus of wafer testing

Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.

Shang-Ju Lee

Papers

Method and apparatus of wafer testing

Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology