Proceedings ArticleDOI
Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology
Hao Chen,Jian-Ting Chen,Shang-Ju Lee,Ken Chou,Cheng-Bin Chen,Sen-Kuei Hsu,Hung-Chih Lin,Ching-Nen Peng,Min-Jer Wang +8 more
- pp 9-12
TLDR
In this paper, a direct probe interface is applied to the post-bond probe in 3D ICs to improve the test reliability and reduce the test cost in the whole test flow.Abstract:
Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.read more
Citations
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Journal ArticleDOI
An overview of through-silicon-via technology and manufacturing challenges
TL;DR: A comprehensive overview of through-silicon-via technology (TSV) is presented, including etch, insulation, and metallization, along with the backside processing, assembly, metrology, design, packaging, reliability, testing and yield challenges that arise with the use of TSVs.
Proceedings ArticleDOI
Contactless Stacked-die Testing for Pre-bond Interposers
TL;DR: This paper proposes to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective and can efficiently improve the yield from 70.5% to 96.84%.
Proceedings ArticleDOI
Cyber physical system (CPS) for contactless IC testing
TL;DR: To improve production yield, a contactless testing with cyber physical system (CPS) for pre-bond interposers is proposed in this paper, and a testing framework comprising a heating laser and an infrared-radiation camera is proposed.
References
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Proceedings ArticleDOI
Testing 3D chips containing through-silicon vias
TL;DR: This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges, and discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wader-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
Proceedings ArticleDOI
A study on package stacking process for package-on-package (PoP)
Akito Yoshida,J. Taniguchi,Kazuyoshi Murata,M. Kada,Y. Yamamoto,Y. Takagi,T. Notomi,A. Fujita +7 more
TL;DR: In this paper, Sharp's chip scale package (top CSP) was mounted on Amkor's bottom CSP to enable package stacking in order to know if packages from two suppliers can get a good solder joint after stacking.
Proceedings ArticleDOI
The leading edge of production wafer probe test technology
TL;DR: In this article, the authors discuss the leading edge practices in three critical areas of wafer test: probe contactor cleaning, I/O pad damage minimization, and sorting good from bad die.
Journal ArticleDOI
Three-dimensional system-in-package using stacked silicon platform technology
TL;DR: In this article, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented.
Journal ArticleDOI
A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method
TL;DR: Based on the conformal mapping technique, a novel macro- π model is proposed to accurately predict the electrical performance of a low pitch-to-diameter ratio (P/D) through-silicon via (TSV) pair on the 3-D IC as discussed by the authors.