An overview of through-silicon-via technology and manufacturing challenges

A stacked-die product integrates multiple dies on interposers. In this paper, we first discuss the difficulties of traditional testing mechanism for interposers. To improve production yield, a contactless testing mechanism for pre-bond interposers is proposed. Our testing mechanism attempts to detect a defective interposer from the thermal image after heating the interposer. We propose to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective. Experimental results show that our testing mechanism can efficiently improve the yield from 70.5% to 96.84%.

Contactless Stacked-die Testing for Pre-bond Interposers

As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks for application/ observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines. The main design objective of the proposed PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed. The PLC receiver is designed and fabricated in CMOS 0.18- $\mu \text{m}$ technology under a supply voltage of 1.8 V. The measurement results show that the receiver can tolerate a voltage drop of up to 0.423 V for a data rate of 10 Mb/s. The power dissipation of the receiver is 3.26 mW under 1.8 V supply, and the core area of the receiver is 74.9 $\mu {\rm m} \times 72.2~\mu \text{m}$ .

Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

Method for reducing contact resistance in semiconductor structures

A three-dimensional integrated circuit including a first layer and a second layer electrically coupled to the first layer and disposed in a stacked relationship relative to the first layer. Logic circuitry is embodied in the first layer and input output circuitry of an input output circuit is embodied in the second layer.

Input output for an integrated circuit

A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.

Test-yield improvement devices for high-density probing techniques and method of implementing the same

Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.

Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology

Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as double TSVs & double μ-bumps schemes. In this paper a novel DFT technique is presented based on the double resource schemes. Challenges to two-die, multi-tier, and numerous interconnects are handled by proposed testable, diag-nosable, repairable, and scalable element, structure, and flow.

A novel DFT architecture for 3DIC test, diagnosis and repair

A novel test module (NTM) for daisy chain test is proposed. In the daisy chain test, the defected chains and components can be easily observed and repaired rapidly by the proposed technology. Besides, the cost of proposed module is much cheaper than the price of tester improvement. Finally, the measured results of the test with NTM are also proposed for verification. The proposed module can save not only debugging time but also the cost in the daisy chain test.

Sen-Kuei Hsu

Papers

Test-yield improvement devices for high-density probing techniques and method of implementing the same

Bandwidth enhancement in 3DIC CoWoS ™ test using direct probe technology

A novel DFT architecture for 3DIC test, diagnosis and repair

A novel test module for interconnect diagnosis enhancement and quality improvement in daisy chain test

Devices for high-density probing techniques and method of implementing the same