Introduction to Electromagnetic Compatibility

Dramatic changes in the physical properties of composites occur when filler particles form a percolating network through the composite, particularly when the difference between the properties of the constitutive phases is large. By use of electric conductivity and dielectric properties as examples, recent studies on the physical properties of composites near percolation are reviewed. The effects of geometric factors and intrinsic properties of the fillers and the matrix, and especially of the interface between fillers and matrix, on electric and dielectric properties near percolation are discussed. Contact resistivity at the interface is less desirable for enhancing electrical conductivity. By contrast, an interface with high resistivity suppresses tunneling between adjacent fillers and leads to percolative composites with higher dielectric constant but lower dielectric loss. This review concludes with an outlook on the future possibilities and scientific challenges in the field.

Physical Properties of Composites Near Percolation

The mechanical flexibility and tunable properties of polymer-based materials make them attractive ones for a lot of applications. Exploring polymer-based dielectrics, such as ones used for capacitors and charge-storage applications, with high dielectric constant (high-j) has recently aroused considerable interest. Especially, motivated by higher function and further miniaturization of electronics, embedding (or integrating) polymer-based capacitors into the inner layers of organic printed circuit boards (PCBs) allows packaging substrate miniaturization and better electrical performance, which is a key for organic-based system-on-package technologies. But as capacitors, the relative dielectric constant j of general polymers (being good insulators) is too low (e.g., j< 5).Thus, a key issue is to substantially raise the dielectric constant of the polymers while retaining low dielectric loss. A few strategies have been developed to raise the j of polymer-based materials. A common approach is to add high-j ceramic fillers (e.g., BaTiO3) into a polymer. High loading of the ceramic fillers in the polymer composite, usually over 50 vol %, can increase j by about ten times relative to the polymer matrix, but dramatically decreases the adhesion of the composite (and increases its porosity) thus deteriorating the adaptability between the composite and the organic circuit boards. Another strategy is to fabricate percolative composite capacitors by using conductive fillers (e.g., metal particles). As the volume fraction f of the fillers increases to the vicinity of the percolation threshold fc, j of the composites can be dramatically enhanced as described by the well-known power law

High Dielectric Performance of Polymer Composite Films Induced by a Percolating Interparticle Barrier Layer

Методы подавления шумов и помех в электронных системах. (Noise reduction techniques in electronic systems)

European Union Risk Assessment Report

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

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Modeling and measurement of simultaneous switching noise coupling through signal via transition

We experimentally demonstrated the great advantages of a high dielectric constant thin film electromagnetic bandgap (EBG) power distribution network (PDN) for the suppression of power/ground noises and radiated emissions in high-performance multilayer digital printed circuit boards (PCBs). Five-layer test PCBs were fabricated and their scattering parameters measured. The power plane noise and radiated emissions were measured, investigated and related to the PDN impedance. This successfully demonstrated that the bandgap of the EBG was extended more than three times, covering a range of hundreds of MHz using a 1-cm /spl times/ 1-cm EBG cell, the SSN was reduced from 170 mV to 10 mV and the radiated emission was suppressed by 22 dB because of the high dielectric constant thin film EBG power/ground network.

High dielectric constant thin film EBG power/ground network for broad-band suppression of SSN and radiated emissions

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.

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Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.

Hyungsoo Kim

Papers

Modeling and measurement of simultaneous switching noise coupling through signal via transition

High dielectric constant thin film EBG power/ground network for broad-band suppression of SSN and radiated emissions

Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs