A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage >

Single-transistor latch in SOI MOSFETs

Changes in technology and device scaling have generally increased the sensitivity of VLSI devices to latchup from single interactions of heavy particles in space. This paper discusses latchup mechanisms, comparing latchup from heavy particles in space with electrically induced latchup, which has been more widely studied. The effects of technology changes and device scaling on latchup susceptibility are discussed as well. Test methods and the interpretation of latchup results are also included, along with predictions of the effects of device evolution and scaling on latchup susceptibility in space.

The influence of VLSI technology evolution on radiation-induced latchup in space systems

Detailed substrate current characteristics of nMOSTs at 4.2 K were obtained with a view to elucidating their transient (hysteresis) and kink behavior below carrier freeze-out. A great similarity with room-temperature behavior is found, indicating that analogous expressions for the substrate current I/sub B/ can be used to calculate the transient time constant that follows from the forced depletion layer formation (FDLF) model reported previously by the authors (see ibid., vol.ED-35, p.1120-5, 1988). In a second part to this work, it will be demonstrated that both the substrate and the cooling bias have a marked influence on the kink. These effects can be fully understood with the FDLF model. >

Freeze-out effects on NMOS transistor characteristics at 4.2 K

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current. >

Modeling of the subthreshold characteristics of SOI MOSFETs with floating body

The articles in this special section focus on computational intelligence for big social data analytics. In the eras of social connectedness and social colonization, people are becoming increasingly enthusiastic about interacting, sharing, and collaborating through online collaborative media. In recent years, this collective intelligence has spread to many different areas, with particular focus on fields related to everyday life such as commerce, tourism, education, and health, causing the size of the Social Web to expand exponentially. The distillation of knowledge from such a large amount of unstructured information, however, is an extremely difficult task, as the contents of today's Web are perfectly suitable for human consumption, but remain hardly understandable to machines. Big social data analysis grows out of this need and combines multiple disciplines such as social network analysis, multimedia management, social media analytics, trend discovery, and opinion mining.

Computational Intelligence for Big Social Data Analysis [Guest Editorial]

The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion. Theoretical expectations for device behavior are presented and corroborated with experimental data; consideration extends to PMOSFET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Examination of n-channel devices, in p-wells, indicates that these are more susceptible to floating well effects, as expected. The primary changes in device behavior include generation of substrate current, slight increase in leakage currents, and some degradation in latchup holding voltage. Results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.

Operation of CMOS devices with a floating well

We suggest a method to estimate the effects of substrate resistances on the latchup holding voltage of CMOS integrated circuits. The estimated holding voltages are shown to be in reasonable agreement with the experimental data inspite of two bold approximations. Using this method, we analyze the effect of several variables relating to the epitaxial substrate and/or the well-isolation trench on the latchup holding voltage. It is shown that there may exist a certain optimum epitaxial layer thickness that leads to a maximum latchup holding voltage and that even a shallow trench is remarkably effective in raising the holding voltage. Physical explanations are offered for the effects of the epitaxial layer and trench on the holding voltage. Examples are presented to illustrate the general effects of several design variables and to aid the design and interpretation of process experiments.

Effects of substrate resistance on CMOS latchup holding voltages

We present an analysis of the latch-up holding voltage of CMOS devices using a lightly doped epitaxially grown layer over a heavily doped substrate, and a well isolation trench of varying depth. Using a simplified simulation scheme it is shown that there exists an optimum epilayer thickness which is somewhat greater than the well depth and leads to maximum holding voltage. Using a relatively shallow trench and with a proper choice of epitaxial layer thickness, the holding voltage can easily be raised above the power supply voltage, thus ensuring freedom from latch-up.

I. Sakai

Papers

Operation of CMOS devices with a floating well

Effects of substrate resistance on CMOS latchup holding voltages

Analysis of latch-up holding voltage for shallow trench CMOS