The role of forward error correction has become of critical importance in fiber optic communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly as poor optical-signal-to-noise environments are encountered. Such environments become more commonplace in higher-speed environments, as more optical amplifiers are deployed in networks. Many generations of FEC have been implemented, including block codes and concatenated codes. Developers now have options to consider hard-decision and soft-decision codes. This article describes the advantages of each type in particular transmission environments.

Forward error correction for 100 G transport networks

Staircase codes, a new class of forward-error-correction (FEC) codes suitable for high-speed optical communications, are introduced. An ITU-T G.709-compatible staircase code with rate R = 239/255 is proposed, and field-programmable-gate-array-based simulation results are presented, exhibiting a net coding gain of 9.41 dB at an output error rate of 10-15, an improvement of 0.42 dB relative to the best code from the ITU-T G.975.1 recommendation. An error floor analysis technique is presented, and the proposed code is shown to have an error floor at 4.0 × 10-21.

Staircase Codes: FEC for 100 Gb/s OTN

Due to the rapid increase in network traffic in the last few years, many telecommunication operators have started transitions to 100-Gb/s optical networks and beyond. However, high-speed optical networks need more efficient forward error correction (FEC) codes to deal with optical impairments, such as uncompensated chromatic dispersion, polarization mode dispersion, and nonlinear effects, and keep the bit error rate (BER) at long distances sufficiently low. To address these issues, new FEC codes, called third-generation codes, have been proposed. A majority of these codes are based on soft-decision decoders and can provide higher coding gain as compared with their predecessors. This paper presents a thorough survey of third-generation FEC codes, suitable for 100 G and beyond optical networks. Furthermore, this paper discusses the main advantages and drawbacks of each scheme and provides a qualitative categorization and comparison of the proposed schemes based on their main features, such as net coding gain and BER. Information about the complexity of each scheme is given as well.

A Survey on FEC Codes for 100 G and Beyond Optical Networks

Modulation formats for 100G and beyond

In this paper, we examine the performance of several modulation formats in more than four dimensions for coherent optical communications systems. We compare two high-dimensional modulation design methodologies based on spherical cutting of lattices and block coding of a ‘base constellation’ of binary phase shift keying (BPSK) on each dimension. The performances of modulation formats generated with these methodologies is analyzed in the asymptotic signal-to-noise ratio regime and for an additive white Gaussian noise (AWGN) channel. We then study the application of both types of high-dimensional modulation formats to standard single-mode fiber (SSMF) transmission systems. For modulation with spectral efficiencies comparable to dual-polarization (DP-) BPSK, polarization-switched quaternary phase shift keying (PS-QPSK) and DP-QPSK, we demonstrate SNR gains of up to 3 dB, 0.9 dB and 1 dB respectively, at a BER of 10−3.

High-dimensional modulation for coherent optical communications systems.

Soft-decision-based forward error correction (FEC) and its practical implementation for 100 Gb/s transport systems are discussed. In applying soft-decision FEC to a digital coherent transponder, we address the configuration of the frame structure of the FEC. For dual-polarized multilevel modulation formats, the keys are having the FEC frames constructed individually for each polarization and a multilane distribution architecture to align each frame. We present two types of soft-decision FEC. One is the concatenation of a Reed-Solomon code and a low-density parity-check (LDPC) code with 2-bit soft decision yielding a Q limit of 7.5 dB. The other, even more powerful, is a triple-concatenated FEC, with a pair of concatenated hard-decision-based block codes further concatenated with a soft-decision-based LDPC code for 20.5% redundancy. We expect that the proposed triple-concatenated codes can achieve a Q limit of 6.4 dB and a net coding gain of 10.8 dB at a post-FEC bit error ratio of 10-15. For the practical implementation of soft-decision FEC for 100 Gb/s systems, we developed field-programmable gate array boards to emulate it. The concept of hardware emulation, with a scalable architecture for the FEC decoder boards, is introduced by way of a pipelined architecture.

Soft-Decision-Based Forward Error Correction for 100 Gb/s Transport Systems

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 90 dB was achieved with 205% redundancy with four iterative decoding for an input bit-error rate of 89 times 10-3 at 313 Gb/s

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

PROBLEM TO BE SOLVED: To provide an error correction device for turning the mark rate of reliability information to 1/2 by a simple low power consumption circuit, executing AC coupling, normally operating CDR for sampling the change point of data, and performing deskew processing as well. SOLUTION: The error correction device includes: a photoelectric converter 1 for converting optical signals from a transmission line to electric signals E; a soft decision identification part 4 for identifying the electric signal E from the photoelectric converter 1 using a plurality of thresholds and generating a plurality of pieces of identification information 4a-4c individually identified by each of the plurality of thresholds; an encoding part 5 for encoding the plurality of pieces of the identification information 4a-4c and generating reliability information 5a and hard decision information 5b; and an FEC decoding part 7 for EXOR-processing or EXNOR-processing the reliability information 5a and the hard decision information 5b and then executing error correction decoding. COPYRIGHT: (C)2011,JPO&INPIT

Inoue Tomoka

Papers

Soft-Decision-Based Forward Error Correction for 100 Gb/s Transport Systems

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

Error correction device