The role of forward error correction has become of critical importance in fiber optic communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly as poor optical-signal-to-noise environments are encountered. Such environments become more commonplace in higher-speed environments, as more optical amplifiers are deployed in networks. Many generations of FEC have been implemented, including block codes and concatenated codes. Developers now have options to consider hard-decision and soft-decision codes. This article describes the advantages of each type in particular transmission environments.

Forward error correction for 100 G transport networks

Staircase codes, a new class of forward-error-correction (FEC) codes suitable for high-speed optical communications, are introduced. An ITU-T G.709-compatible staircase code with rate R = 239/255 is proposed, and field-programmable-gate-array-based simulation results are presented, exhibiting a net coding gain of 9.41 dB at an output error rate of 10-15, an improvement of 0.42 dB relative to the best code from the ITU-T G.975.1 recommendation. An error floor analysis technique is presented, and the proposed code is shown to have an error floor at 4.0 × 10-21.

Staircase Codes: FEC for 100 Gb/s OTN

The Industrial Internet of Things (IIoT) is a crucial research field spawned by the Internet of Things (IoT). IIoT links all types of industrial equipment through the network; establishes data acquisition, exchange, and analysis systems; and optimizes processes and services, so as to reduce cost and enhance productivity. The introduction of edge computing in IIoT can significantly reduce the decision-making latency, save bandwidth resources, and to some extent, protect privacy. This paper outlines the research progress concerning edge computing in IIoT. First, the concepts of IIoT and edge computing are discussed, and subsequently, the research progress of edge computing is discussed and summarized in detail. Next, the future architecture from the perspective of edge computing in IIoT is proposed, and its technical progress in routing, task scheduling, data storage and analytics, security, and standardization is analyzed. Furthermore, we discuss the opportunities and challenges of edge computing in IIoT in terms of 5G-based edge communication, load balancing and data offloading, edge intelligence, as well as data sharing security. Finally, we introduce some typical application scenarios of edge computing in IIoT, such as prognostics and health management (PHM), smart grids, manufacturing coordination, intelligent connected vehicles (ICV), and smart logistics.

Edge Computing in Industrial Internet of Things: Architecture, Advances and Challenges

We examine analog-to-digital and digital-to-analog converters (ADCs and DACs), as well as digital signal processing (DSP) functions for optical coherent modems.

Advances in High-Speed DACs, ADCs, and DSP for Optical Coherent Transceivers

Due to the rapid increase in network traffic in the last few years, many telecommunication operators have started transitions to 100-Gb/s optical networks and beyond. However, high-speed optical networks need more efficient forward error correction (FEC) codes to deal with optical impairments, such as uncompensated chromatic dispersion, polarization mode dispersion, and nonlinear effects, and keep the bit error rate (BER) at long distances sufficiently low. To address these issues, new FEC codes, called third-generation codes, have been proposed. A majority of these codes are based on soft-decision decoders and can provide higher coding gain as compared with their predecessors. This paper presents a thorough survey of third-generation FEC codes, suitable for 100 G and beyond optical networks. Furthermore, this paper discusses the main advantages and drawbacks of each scheme and provides a qualitative categorization and comparison of the proposed schemes based on their main features, such as net coding gain and BER. Information about the complexity of each scheme is given as well.

A Survey on FEC Codes for 100 G and Beyond Optical Networks

Soft-decision-based forward error correction (FEC) and its practical implementation for 100 Gb/s transport systems are discussed. In applying soft-decision FEC to a digital coherent transponder, we address the configuration of the frame structure of the FEC. For dual-polarized multilevel modulation formats, the keys are having the FEC frames constructed individually for each polarization and a multilane distribution architecture to align each frame. We present two types of soft-decision FEC. One is the concatenation of a Reed-Solomon code and a low-density parity-check (LDPC) code with 2-bit soft decision yielding a Q limit of 7.5 dB. The other, even more powerful, is a triple-concatenated FEC, with a pair of concatenated hard-decision-based block codes further concatenated with a soft-decision-based LDPC code for 20.5% redundancy. We expect that the proposed triple-concatenated codes can achieve a Q limit of 6.4 dB and a net coding gain of 10.8 dB at a post-FEC bit error ratio of 10-15. For the practical implementation of soft-decision FEC for 100 Gb/s systems, we developed field-programmable gate array boards to emulate it. The concept of hardware emulation, with a scalable architecture for the FEC decoder boards, is introduced by way of a pipelined architecture.

Soft-Decision-Based Forward Error Correction for 100 Gb/s Transport Systems

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 90 dB was achieved with 205% redundancy with four iterative decoding for an input bit-error rate of 89 times 10-3 at 313 Gb/s

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

Provided is a multi-value optical transmitter in which a DC bias may be controlled to be stabilized so as to obtain stable optical transmission signal quality in multi-value modulation using a dual-electrode MZ modulator The multi-value optical transmitter includes: D/A converters for performing D/A conversion on first and second modulation data which are set based on an input data series, so as to generate a first and a second multi-value signal, respectively; a dual-electrode MZ modulator including phase modulators for modulating light from a light source based on the first multi-value signal and the second multi-value signal, so as to combine optical signals from the phase modulators to output the optical multi-value signal; an optical output power monitor for detecting average power of the optical multi-value signal; and a DC bias control unit for controlling a DC bias for the dual-electrode MZ modulator, so as to maximize the average power

Multi-value optical transmitter

Electronic pre-equalization for 43 Gb/s DQPSK has been demonstrated for the first time. Waveform distortion caused by bandwidth narrowing to 18.1 GHz by cascaded 10 Gb/s ROADMs has been adequately pre-equalized by a SiGe-BiCMOS LSI with 6-bit, 43 GS/s digital-to-analog converters.

Soichiro Kametani

Papers

Soft-Decision-Based Forward Error Correction for 100 Gb/s Transport Systems

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

Multi-value optical transmitter

43 Gb/s DQPSK pre-equalization employing 6-bit, 43GS/s DAC integrated LSI for cascaded ROADM filtering

43 Gb/s DQPSK pre-equalization employing 6-bit, 43GS/s DAC integrated LSI for cascaded ROADM filtering