In this paper we present a reconfigurable routing algorithm for a 2D-mesh network-on-chip (NoC) dedicated to fault- tolerant, massively parallel multi-processors systems on chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router).

/pdf/a-reconfigurable-routing-algorithm-for-a-fault-tolerant-2d-1r0vyhd8pi.pdf

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

The distribution of a synchronous clock in system-on-chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the globally asynchronous, locally synchronous try to solve this issue by partitioning the SoC into isolated synchronous islands. This paper describes the bisynchronous FIFO used on the DSPIN network-on-chip capable to interface systems working with different clock signals (frequency and/or phase). Its interfaces are synchronous and its architecture is scalable and synthesizable in synchronous standard cells. The metastability situations and its latency are analyzed. Its throughput, maximum frequency, and area are evaluated in function of the FIFO depth.

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput bounds. Traditionally, NoC architectures only deliver scalability on two of the aforementioned three levels, or do not offer GS. In this paper we present the composable and predictable aelite NoC architecture, that offers only GS, based on flit-synchronous Time Division Multiplexing (TDM). In contrast to other TDM-based NoCs, scalability on the physical level is achieved by using mesochronous or asynchronous links. Functional scalability is accomplished by completely isolating applications, and by having a router architecture that does not limit the number of service levels or connections. We demonstrate how aelite delivers the requested service to hundreds of simultaneous connections, and does so with 5 times less area compared to a state-of-the-art NoC.

/pdf/aelite-a-flit-synchronous-network-on-chip-with-composable-h6gad5b853.pdf

aelite: a flit-synchronous network on chip with composable and predictable services

In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result in a design in which data are transferred in a pipelined fashion, from the local memory of the sending core to the local memory of the receiving core, without any dynamic arbitration, buffering, and clock synchronization. The routers use two-phase bundled-data handshake latches based on the Mousetrap latch controller and are extended with a clock gating mechanism to reduce the energy consumption. The NIs integrate the direct memory access functionality and the TDM schedule, and use dual-ported local memories to avoid buffering, flow-control, and synchronization. To verify the design, we have implemented a 4 $\times $ 4 bitorus NoC in 65-nm CMOS technology and we present results on area, speed, and energy consumption for the router, NI, NoC, and postlayout.

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

QNoC asynchronous router

The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture DSPIN is a scalable packet switching micro-network dedicated to GALS (Globally Asynchronous, Locally Synchronous) clustered, multi-processors, systems on chip The DSPIN architecture has a very small foot-print and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

A control device is provided for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system. The control device includes a write pointer and a read pointer. The control device also includes a write management circuit and a read management circuit. The write management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a write operation in the memory. The read management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a read operation in the memory.

Control device for controlling a buffer memory

Ce papier presente le micro-reseau DSPIN qui est une evolution de l'architecture SPIN. DSPIN est un micro-reseau a commutation de paquets pour architectures multiprocesseurs integres sur puce (MPSoC) utilisant l'approche GALS (Globalement Asynchrone, Localement Synchrone). L'architecture de DSPIN a une surface de silicium tres petite et fournit des canaux de communication avec garanties de latence et de bande passante pour des applications soumises a des contraintes temps-reel.

Micro-réseau sur puce compatible avec l'approche GALS

The device has write and read managing circuits for comparing a content of a write pointer e.g. n bit shift register, and a content of a read pointer such as n bit shift register, and for authorizing and avoiding the authorization to respectively write and read in a buffer. A synchronization circuit (54) has an adjustable delay circuit (541) that is adjusted when clock signals associated with two electronic systems have same frequency but are out of phase with respect to one another, such that active edges of a delayed clock signal are off set with active edges of the clock signals.

Circular buffer controlling device for memorizing data word, has delay circuit adjusted when clock signals associated with systems have same frequency, such that edges of delayed clock signal are off set with edges of clock signals

Ivan Miro Panades

Papers

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Control device for controlling a buffer memory

Micro-réseau sur puce compatible avec l'approche GALS

Circular buffer controlling device for memorizing data word, has delay circuit adjusted when clock signals associated with systems have same frequency, such that edges of delayed clock signal are off set with edges of clock signals