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Alain Greiner
Researcher at Pierre-and-Marie-Curie University
Publications - 78
Citations - 2557
Alain Greiner is an academic researcher from Pierre-and-Marie-Curie University. The author has contributed to research in topics: System on a chip & Network on a chip. The author has an hindex of 19, co-authored 78 publications receiving 2474 citations. Previous affiliations of Alain Greiner include University of Paris & Sorbonne.
Papers
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Proceedings ArticleDOI
A generic architecture for on-chip packet-switched interconnections
Pierre Guerrier,Alain Greiner +1 more
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
Proceedings ArticleDOI
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
Adrijean Adriahantenaina,Hervé Charlery,Alain Greiner,Laurent Mortiez,Cesar Albenes Zeferino +4 more
TL;DR: The SPIN micro-network is presented that is a generic, scalable interconnect architecture for system on chip that provides a simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators and targets.
Proceedings ArticleDOI
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures
I. Miro Panades,Alain Greiner +1 more
TL;DR: The bisynchronous FIFO used on the DSPIN network-on-chip capable to interface systems working with different clock signals (frequency and/or phase) and its architecture is scalable and synthesizable in synchronous standard cells is described.
Proceedings ArticleDOI
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach
TL;DR: The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture, a scalable packet switching micro- network dedicated to GALS clustered, multi-processors, systems on chip.
Journal ArticleDOI
A portable clock multiplier generator using digital CMOS standard cells
TL;DR: This paper presents a circuit fabricated to test a new method of clock frequency multiplication that uses a digital CMOS process in order to implement the delay locked loop and does not require external components.