This paper presents a new high-gain structure for the distributed amplifier. Negative capacitance cells are exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the distributed amplifier while keeping the desired bandwidth. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplifier bandwidth. Implemented in 0.13-μm IBM's CMRF8SF CMOS, the proposed six-stage distributed amplifier presents an average gain of 13.2 dB over a bandwidth of 29.4 GHz. The measured input return loss is less than -9 dB and the output return loss is less than -9.5 dB over the entire bandwidth. With a chip area of 1.5 mm × 0.8 mm, the amplifier consumes 136 mW from a 1.5-V dc power supply.

Gain-Enhanced Distributed Amplifier Using Negative Capacitance

This letter presents an ultra-wideband distributed amplifier (DA) implemented in a 250 nm InP HBT technology. Four cascode gain cells are distributed along the input and output microstrip lines to achieve wideband operation. Each cascode cell employs inductive peaking at the output to further enhance the bandwidth and to align the phase delay between the input and output lines. All dc bias components are fully integrated on-chip. The DA exhibits a measured gain of 10 dB with a 3 dB bandwidth extending from 40 to 222 GHz. The maximum output power was measured to be 6.0, 9.2, and 8.5 dBm at 60, 77, and 134 GHz, respectively, which allows the DA to also be used as a medium-power amplifier. To the authors' best knowledge, the DA achieves the highest 3 dB bandwidth of 182 GHz reported thus far, while showing low dc power consumption (105 mW) compared to other state-of-the-art DAs.

A Fully-Integrated 40–222 GHz InP HBT Distributed Amplifier

This paper presents CMOS distributed amplifiers (DAs) using the proposed gate-drain transformer feedback technique. The feedback allows reuse of the traveling signal to achieve a high gain-bandwidth product while maintaining low power consumption of DAs. With the folded transmission lines and patterned ground shield, the miniaturized transformer has high quality factors and a well-controlled feedback coupling coefficient. Two DAs are realized using the proposed technique in both 0.18-μm and 90-nm CMOS technologies, respectively. The 0.18-μm CMOS DA achieves a gain of 9.5 dB with a 3-dB bandwidth of 32 GHz, and the noise figure (NF) ranges from 4.1 to 7.6 dB under a power consumption of 71 mW. Under a power consumption of 60 mW, the 90-nm DA demonstrates a gain of 7 dB, a bandwidth of 61.3 GHz, and an NF below 6.2 dB up to 40 GHz. The core areas of the 0.18-μm and 90-nm designs are only 0.58 and 0.41 mm2, respectively.

CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

Mon projet de recherche s'applique en premier lieu a developper et adapter les activites sur lesquelles je travaille depuis 14 ans, a savoir la conception et la realisation de circuits (amplificateurs et filtres) micro-ondes pour des applications embarquees sur les repeteurs satellite Pour illustrer cette volonte, j'ai expose deux des themes de recherche (filtres multimodes en bande Ka et amplificateur de puissance a ondes travelling sur substrat silicium), sachant que j'aurai pu egalement evoquer le fait d'appliquer la methode des frequences reelles au traitement des frequences harmoniques pour les amplificateurs fortement non-lineaires de puissance Les autres axes de recherche presentes sont tous dans le domaine de la conception de circuits dits radiofrequences La particularite de ces circuits a application telephonie mobile ou WLAN se situe au niveau des nouvelles techniques de conception qui different de l'approche classique du concepteur analogique ; en effet, elles font souvent intervenir des caracterisations electromagnetiques afin d'extraire des modeles electriques equivalents (balun, resonateur BAW) De plus, la montee en frequence pour certaine des applications RF, autorisant des debits plus grands et donc des bandes passantes plus large (UWB), ou encore les systemes multi-bande et multi-mode (GSM, DCS, PCS WCDMA, bluetooth) necessitent des circuits d'adaptation multi-bande ou large bande dont certains pourront directement s'inspirer des architectures micro-ondes existantes Mon projet de recherche consiste donc a appliquer une approche micro-onde a la conception de circuits integres sur silicium Il ne s'agit evidemment pas de la substituer a l'approche analogique classique, mais au contraire a rendre les deux approches complementaires, afin qu'elles s'en enrichissent

https://tel.archives-ouvertes.fr/tel-00401318/document

Contribution à la Conception de Circuits Microondes et Radiofréquences

The structure of the modern wireless network evolves rapidly and maturing 4G networks pave the way to next generation 5G communication. A tendency of shifting from traditional high-power tower-mounted base stations towards heterogeneous elements can be spotted, which is mainly caused by the increase of annual wireless users and devices connected to the network. The radio frequency (RF) power amplifier (PA) performance directly affects the efficiency of any transmitter, therefore, the emerging 5G cellular network requires new PA architectures with improved efficiency without sacrificing linearity. A review of the most promising reported RF PA architectures is presented in this article, emphasizing advantages, disadvantages and concluding with a quantitative comparison. The main scope of reviewed papers are PAs implemented in scalable complementary metal–oxide–semiconductor (CMOS) and SiGe BiCMOS processes with output powers suitable for portable wireless devices under 32 dBm (1.5 W) in the low- and high- 5G network frequency ranges.

A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks

This paper describes two single-ended three-stage SiGe HBT distributed amplifiers employing constant-k filter sections, m-derived filter sections, and a metal or a deep-trench ground plane in the artificial transmission lines. The distributed amplifiers exhibit a measured passband of 100 MHz-50 GHz; they have a small die size (1.0/spl times/1.1 mm/sup 2/) and low power consumption (125 mW). The measured results demonstrate that distributed amplifiers in SiGe can be competitive with those in III-V processes.

50-GHz SiGe HBT distributed amplifiers employing constant-k and m-derived filter sections

This paper describes a single-ended five-stage CMOS distributed amplifier employing m-derived filter sections in the artificial transmission lines. The distributed amplifier exhibits a measured pass-band gain of 8.8 + 1 dB for a 5 V rail, and a bandwidth of 45 MHz to 29.5 GHz with a unity gain bandwidth of 32.5 GHz. The die size is 0.85 x 1.0 mm2. The amplifier exhibits a peak-to-peak output voltage of 2.4 V. This amplifier is suitable for use in communication systems.

A 2.4Vp-p output, 0.045-32.5 GHz CMOS Distributed Amplifier

This paper describes a single-ended three-stage SiGe HBT distributed amplifier employing constant-k, m-derived filter sections in the output artificial transmission line. The distributed amplifier exhibits a measured passband of 100 MHz to 50 GHz, has a small die size (1.0 /spl times/ 1.1 mm/sup 2/) and low power consumption (125 mW). This amplifier is suitable for use in communication systems.

http://ieeexplore.ieee.org/iel5/8599/27270/01212520.pdf

J. Aguirre

Papers

50-GHz SiGe HBT distributed amplifiers employing constant-k and m-derived filter sections

A 2.4Vp-p output, 0.045-32.5 GHz CMOS Distributed Amplifier

A 0.1 - 50 GHz SiGe HBT distributed amplifier employing constant-k m-derived sections