Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

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Review: Semiconductor Piezoresistance for Microsystems

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

(Vol. 1, part of 2 vols set) Size: 22x14cm., Contents: Chapter I. Tension and Compression within the Elastic Limit II. Analysis of Stress and Strain III. Bending Moment and Shearing Force IV. Stresses in Laterally Loaded Symmetrical beams V. Deflection of Laterally Loaded Symmetrical Beams VI. Statically Indeterminate Problems in Bending VII. Symmetrical Beams of Variable Cross Section-Beams of Two Materials VIII. Bending of Beams in a plane which is not a Plane of Symmetry IX. Combined Bending and Axial Load Theory of Columns X. Torsion and Combined Bending and Torsion XI. Strain Energy and Impact XII. Curved Bars Appendix A: Moments of Inertia of Plane Areas Appendix B. Tables of Structural Shapes Author Index Subject Index. ISBN:8123910304 xiv+442 Yr. of Pub.reprint 2004Paper Back

Strength of materials ..

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

Silicon (Si) and/or germanium (Ge) nanomembranes (NMs) play crucial roles in various applications, including conventional microelectronics, as well as recently emerging high-performance flexible/stretchable electronics. Because of their superior mechanical properties, such as flexibility, strain-ability, and bond-ability, Si/GeNMs can be strain-engineered, functionalized, and assembled into two/three-dimensional (2D/3D) micro/nano-architectures and devices. These features offer significant opportunities in nanoscience and for the development of nanotechnology. Strain engineering of semiconductor NMs enables the modification of their physical properties, in particular those of Si and Ge (e.g., carrier mobility, band structure), thus creating enormous potential for use in high-speed rigid/flexible electronics, optoelectronics, and nanophotonics. The mechanical properties of NMs allow large deformations at the micro/nano-scale, via self-assembly or guided self-assembly, leading to 3D micro/nano-architectures, including tubes, wrinkles, buckles, and mesostructures. The transformation from 2D planar NMs to 3D micro/nano-architectures again strongly influences physical properties (e.g., mechanics, optics, and electronics), providing fascinating applications in sensing, energy harvesting, bio-integration, and flexible/stretchable electronics. In this Review, the recent progress in strain engineering and mechanical assembly of Si/GeNMs is reviewed, ranging from fundamental principles to device applications.

Strain engineering and mechanical assembly of silicon/germanium nanomembranes

A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to ~700 MPa of process-induced stress. This provides the highest uniaxial channel stress to date at ~1.5 GPa. The stress altered drain-current is measured for long and short (50-140 nm) devices and the extracted pi-coefficients are observed to be approximately constant for stresses up to ~1.5 GPa. For short devices, this trend is seen only after correcting for the significant degradation in the pi-coefficients observed due to parasitic source/drain series resistances (Rsd/)

J.C. Ziegert

Papers

Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ( $\sim$ 1.5 GPa) Channel Stress