We describe Delta-I noise caused by power plane resonances in multilayer boards. First, we study the effect of power plane resonances on the ground bounce of the system by performing finite-difference time-domain (FDTD) simulations. We simulate the voltage fluctuations at one point of the printed circuit board (PCB) due to a current surge between the power planes in a different point. Next, two methods to prevent this ground bounce effect are investigated. The first method consists of adding lumped capacitances to the design. The effect of one large capacitor is compared to the effect of adding a "wall" of smaller capacitors. A second approach is to isolate the chips by etching a slot around the sensitive integrated circuits (ICs) and connecting both sides by a small inductor. Both methods provide excellent protection against power plane resonances.

Study of the ground bounce caused by power plane resonances

The significance of interconnect parasitics of power electronics systems is their effects on power converters' electromagnetic interference (EMI)-related performances, such as voltage/current spikes, dv/dt, di/dt, conducted/radiated EMI noise, etc. In this paper, a time domain reflectometry (TDR) measurement-based modeling technique is described for characterizing interconnect parasitics in switching power converters. Experiments are conducted on power components of a prototype high-power inverter, including insulated gate bipolar transistor (IGBT) modules, busbar and bulk capacitors. It is shown that the interconnect inductance of the IGBT module can be extracted completely using TDR. It is also shown that the busbar equivalent circuit can be modeled as transmission line segments or L-C filter sections, and the bulk capacitor contains a significant equivalent series interconnect inductance.

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Characterization of power electronics system interconnect parasitics using time domain reflectometry

Differential signaling has become a popular choice for multigigabit digital applications in favor of its low-noise generation and high common-mode noise immunity. Recalling from the full-wave solution of S-parameters, this paper presented a design methodology of analysis scheme to extract the equivalent circuits of discontinuities observed on the strongly coupled differential lines. Signal integrity effects of the bent differential transmission lines in a high-speed digital circuit were then simulated in the time domain. A dual back-to-back routing topology of bent differential lines to reduce the common-mode noise was further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance was also proposed. Furthermore, the comparison between the simulation and measured results validated the equivalent circuit model, coupled bends with compensation capacitance patch, and analysis approach

Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines

A technique for the equivalent circuit modeling of interconnects having discontinuities such as bends, steps, and junctions in high-speed circuits and packages is developed. The circuit models are extracted from time domain reflection (TDR) measurements. The simulated results for the circuit models are compared with the measured data to validate the accuracy of the circuit model. The proposed method can be used to help validate circuit models based on field-theoretic techniques as well as used as an independent tool to synthesize circuit models for general nonuniform or interacting two- and three-dimensional interconnects. >

Equivalent circuit modeling of interconnects from time domain measurements

Traditional methods used to monitor interconnect reliability are based on measurement of dc resistance. DC resistance is well suited for characterizing electrical continuity, such as identifying an open circuit, but is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates toward the interior. At frequencies above several hundred megahertz, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Due to the skin effect, RF impedance monitoring offers a more sensitive and reproducible means of sensing interconnect degradation than dc resistance. Since the operation of many types of electronic product requires transmission of signals with significant frequency components in the gigahertz range, this has the further implication that even a small crack at the surface of an interconnect may adversely affect the performance of current and future electronics. This paper demonstrates the value of RF impedance measurements as an early indicator of physical degradation of solder joints as compared to dc-resistance measurements. Mechanical fatigue tests have been conducted with an impedance-controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of dc resistance and time domain reflection coefficient as a measure of RF impedance while the solder joints were stressed. The RF impedance was observed to increase in response to the early stages of cracking of the solder joint while the dc resistance remained constant. Failure analysis revealed that the RF impedance increase resulted from a physical crack, which initiated at the surface of the solder joint and propagated only partway across the solder joint. A comparison between RF impedance and event detectors was made to compare their respective sensitivities in detecting interconnect degradation. These test results indicate that RF impedance can serve as a nondestructive early indicator of solder joint degradation and as an improved means for assessing reliability of high-speed electronics.

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Early Detection of Interconnect Degradation by Continuous Monitoring of RF Impedance

Experimental techniques to characterize typical interconnect discontinuities such as bends and steps, based on time-domain reflection (TDR) measurements, are formulated. These interconnect discontinuities are characterized in terms of general lumped/distributed circuit models which are compatible with CAD simulation tools such as SPICE. The results for the model element values are shown to be consistent with frequency-domain lumped equivalent models for microstrips derived from S-parameter measurements and electromagnetic computations based on the excess inductance and capacitance concepts. The models are also validated by simulating their step response on SPICE and comparing them with the TDR data. >

Time-domain characterization of interconnect discontinuities in high-speed circuits

The dynamic deconvolution (peeling algorithm) used in the past for single interconnects is extended to multiple-coupled interconnects and used to model high-speed electronic packages. A multilayer ceramic package (MLC) is used as vehicle to demonstrate the characterization and equivalent circuit modeling procedure based on single and multiport time-domain measurement.

Time-domain characterization and circuit modeling of a multilayer ceramic package

A frequency-dependent nonuniform transmission line model for parallel semi-infinite conducting power/ground planes is presented. The model is validated by comparing the calculated time domain response with the measured time domain reflectometer (TDR) data. >

A model for parallel semi infinite conducting planes

In this paper, a circuit modeling technique based on time domain measurements for power/ground systems in electronic packages is presented. Equivalent circuit model of power/ground systems for an MLC package is then incorporated with the circuit model of high speed digital drivers for switching noise simulation.

J.M. Jong

Papers

Equivalent circuit modeling of interconnects from time domain measurements

Time-domain characterization of interconnect discontinuities in high-speed circuits

Time-domain characterization and circuit modeling of a multilayer ceramic package

A model for parallel semi infinite conducting planes

Modeling and simulation of switching noise with the associated package resonance for high speed digital circuits