Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore’s law (i.e. More Moore) and More than Moore scaling. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0051501jss] All rights reserved.

https://iopscience.iop.org/article/10.1149/2.0051501jss/pdf

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

This paper presents an in-depth overview of the application and impact of UV/VUV light in advanced interconnect technology. UV light application in BEOL historically was mainly motivated by the need to remove organic porogen and generate porosity in organosilicate (OSG) low-k films. Porosity lowered the film's dielectric constant, k, which enables one to reduce the interconnect wiring capacitance contribution to the RC signal delay in integrated circuits. The UV-based low-k film curing (λ > 200 nm) proved superior to thermal annealing and electron beam curing. UV and VUV light also play a significant role in plasma-induced damage to pSiCOH. VUV light with λ < 190–200 nm is able to break Si-CH3 bonds and to make low-k materials hydrophilic. The following moisture adsorption degrades the low-k properties and reliability. This fact motivated research into the mechanisms of UV/VUV photon interactions in pSiCOH films and in other materials used in BEOL nanofabrication. Today, the mechanisms of UV/VUV photon interactions with pSiCOH and other films used in interconnect fabrication are fairly well understood after nearly two decades of research. This understanding has allowed engineers to both control the damaging effects of photons and utilize the UV light for material engineering and nanofabrication processes. Some UV-based technological solutions, such as low-k curing and UV-induced stress engineering, have already been widely adopted for high volume manufacturing. Nevertheless, the challenges in nanoscaling technology may promote more widespread adoption of photon-assisted processing. We hope that fundamental insights and prospected applications described in this article will help the reader to find the optimal way in this wide and rapidly developing technology area.

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Impact of VUV photons on SiO2 and organosilicate low-k dielectrics: General behavior, practical applications, and atomic models

Activation of electroplated-Cu surface via plasma pretreatment for low temperature Cu-Sn bonding in 3D interconnection

A semiconductor device according to the present invention includes a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall, a gate insulating film formed on the sidewall and the bottom wall of the gate trench, and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, while the semiconductor layer includes a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench, a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench, a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench.

Semiconductor device and method for producing same

Effective Cu surface pre-treatment for high-reliable 22nm-node Cu dual damascene interconnects with high plasma resistant ultra low-k dielectric (k=2.2)

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k∼2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

J. Protzman

Papers

Effective Cu surface pre-treatment for high-reliable 22nm-node Cu dual damascene interconnects with high plasma resistant ultra low-k dielectric (k=2.2)

Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules