Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

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System level analysis of fast, per-core DVFS using on-chip switching regulators

THIS paper explores opportunities and challenges in power conversion in the VHF frequency range of 30-300 MHz. The scaling of magnetic component size with frequency is investigated, and it is shown that substantial miniaturization is possible with increased frequencies even considering material and heat transfer limitations. Likewise, dramatic frequency increases are possible with existing and emerging semiconductor devices, but necessitate circuit designs that either compensate for or utilize device parasitics. We outline the characteristics of topologies and control methods that can meet the requirements of VHF power conversion, and present supporting examples from power converters operating at frequencies of up to 110 MHz.

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Opportunities and Challenges in Very High Frequency Power Conversion

Three-dimensional integration is an emerging fabrication technology that vertically stacks multiple integrated chips. The benefits include an increase in device density; much greater flexibility in routing signals, power, and clock; the ability to integrate disparate technologies; and the potential for new 3D circuit and microarchitecture organizations. This article provides a technical introduction to the technology and its impact on processor design. Although our discussions here primarily focus on high-performance processor design, most of the observations and conclusions apply to other microprocessor market segments.

Processor Design in 3D Die-Stacking Technologies

Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converter's efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9 % for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

This paper reviews the current state of power supply technology platforms and highlights future trends and challenges toward realizing fully monolithic power converters. This paper presents a detailed survey of relevant power converter technologies, namely power supply in package and power supply on chip (PwrSoC). The performance of different power converter solutions reported in the literature is benchmarked against existing commercial products. This paper presents a detailed review of integrated magnetics technologies, primarily microinductors, a key component in realizing a monolithic power converter. A detailed review and comparison of different microinductor structures and the magnetic materials used as inductor cores is presented. The deposition techniques for integrating the magnetic materials in the microinductor structures are discussed. This paper proposes the use of two performance metrics or figures of merit in order to compare the dc and ac performance of individual microinductor structures. Finally, the authors discuss future trends, key challenges, and potential solutions in the realization of the “holy grail” of monolithically integrated power supplies (PwrSoC).

Review of Integrated Magnetics for Power Supply on Chip (PwrSoC)

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

According to some embodiments, a plurality of single-phase hysteretic converters operate in accordance with associated synchronization signals.

Hysteretic DC-DC converters

We demonstrate an integrated buck DC-DC converter implemented in a 90nm CMOS technology for multi-Vcc microprocessors. High switching frequency (100-317MHz), 4-phase topology, and fast hysteretic control reduce inductor and capacitor sizes by 1000x, thereby enabling off-chip inductors with no magnetic core and an on-chip decoupling capacitor. The converter achieves 80-87.7% efficiency and 10% peak-to-peak output noise.

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

A buffer circuit includes a resonant circuit. An output of the resonant buffer circuit transitions once for three transitions on an input.

Jae-Hong Hahn

Papers

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Hysteretic DC-DC converters

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

Resonant buffer apparatus, method, and system