This paper proposes the modified radix-2/sup 4/ and the radix-4/sup 2/ FFT algorithms and efficient pipeline FFT architectures based on those algorithms for OFDM systems. The proposed pipeline FFT architectures have the same number of multipliers as that of the conventional R2/sup 2/SDF and R4SDC. However, the multiplication complexity and the ROMs for storing twiddle factors could be reduced by more than 30% and 50% respectively by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 /spl mu/m CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area and power efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

http://ieeexplore.ieee.org/iel5/10549/33371/01579923.pdf

Area and power efficient pipeline FFT algorithm

An N-symbol discrete Fourier transform (N -DFT) processor based on analog CMOS current mirrors that operate in the strong inversion region is presented. It is shown that transistor mismatch can be modeled as an input-referred noise source that can be used in system-level studies. Simulations of a radix-2, 256-symbol fast Fourier transform (FFT) show that the model produces equivalent results to those of a model that incorporates a mismatch term into each current mirror. It is shown that in general, high-radix FFT structures and specifically the full-radix DFT have reduced sensitivity to mismatch and a reduced number of current mirrors compared to radix-2 structures and have some key advantages in terms of transistor count with respect to comparable digital implementations. Simulations of an orthogonal frequency-division multiplexing system with forward error control coding, that take into account current mirror nonidealities such as mismatch, show that an analog DFT front end loses only 0.5 dB with respect to an ideal circuit.

Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis

In the warming world, tropical Pacific sea surface temperature (SST) variation has received considerable attention because of its enormous influence on global climate change, particularly the El Nino-Southern Oscillation process. Here, we provide new high-resolution proxy records of the magnesium/calcium ratio and the oxygen isotope in foraminifera from a core on the Ontong-Java Plateau to reconstruct the SST and hydrological variation in the center of the Western Pacific Warm Pool (WPWP) over the last 360 000 years. In comparison with other Mg/Ca-derived SST and δ18O records, the results suggested that in a relatively stable condition, e.g., the last glacial maximum (LGM) and other glacial periods, the tropical Pacific would adopt a La Nina-like state, and the Walker and Hadley cycles would be synchronously enhanced. Conversely, El Nino-like conditions could have occurred in the tropical Pacific during fastchanging periods, e.g., the termination and rapidly cooling stages of interglacial periods. In the light of the sensitivity of the Eastern Pacific Cold Tongue (EPCT) and the inertia of the WPWP, we hypothesize an inter-restricted relationship between the WPWP and EPCT, which could control the zonal gradient variation of SST and affect climate change.

Correspondence between the ENSO-like state and glacial-interglacial condition during the past 360 kyr

This paper proposes a new efficient FFT architecture with structured pipeline for OFDM systems, based on radix-2/sup 4/ algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2/sup 2/ algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multiplier can enhance the area/power efficiency of the design. From synthesis simulations of a standard 0.35/spl mu/m CMOS process, it achieved above 60% area reduction when compared with the conventional programmable multiplier.

Fast Fourier transform processor based on low-power and area-efficient algorithm

A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

Canonical signed digit multiplier

In this paper, a new Radix-N pipeline fast Fourier transform (FFT) processor for the implementation of IEEE 802.11a baseband orthogonal frequency division multiplexing (OFDM) modem for wireless local area network (WLAN) is proposed. The newly proposed scheme has a simple control structure and multiplication block is designed based on canonic signed digit (CSD) with N/4 twiddle factors, which enables both hardware complexity and power consumption to be reduced as about less 33% and 66% respectively than the conventional Radix-4 pipeline and Radix-2 pipeline structures. In order to verify the real time operation, the IEEE802.11a baseband OFDM test-bed with the newly proposed Radix-N pipeline FFT processor is implemented using field programmable gate array (FPGA) devices.

https://iopscience.iop.org/article/10.1143/JJAP.42.2176/pdf

Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor

We propose a design method of fast Fourier transform (FFT) large-scaled integration (LSI) for an orthogonal frequency division multiplexing (OFDM) system. The proposed FFT LSI is designed with simple current mode circuits, wired-OR connection and gate-width-ratioed current mirror. For a low power consumption, two design methods are proposed, current-cut (CC) and rounding process. The CC operation is performed with on-off operation of a current source. The rounding process is adopted for the component of the FFT matrix. Bit error rate (BER) in the OFDM system is simulated from "0.1" rounding step to "1.0". The BER performance of the FFT matrix with the "0.2" rounding step has little degradation from that of the original FFT matrix. The 8-point FFT LSI with the "0.2" rounding step is designed and implemented using a 0.8 µm complementary metal-oxide semiconductor (CMOS) technology. On the basis of measurement of the 8-point FFT LSI, the power consumption of the 64-point FFT LSI using CC can be estimated as being less than 10 mW.

Novel FFT LSI for Orthogonal Frequency Division Multiplexing Using Current Mode Circuit

We have proposed an intracell reverse link of an SS-CDMA flexible wireless network based on an approximately synchronized (AS) CDMA. The AS-CDMA features no co-channel interference during a guard-chip duration. A sequence with the guard-chip duration can be designed using the pseudo periodic method and the orthogonal frequency multi-channel method. The reverse link without co-channel interference does not require the sophisticated transmission power control, which is indispensable in the conventional systems such as IS-95. The AS-CDMA modem has been designed and implemented for the Japanese 2.4 GHz SS band. An AS-CDMA sequence of length 48 is designed. The number of the orthogonal frequency multi-channel method is 2. One of the features of the implemented reverse link modem is the use of a surface-acoustic-wave convolver as a correlator for rapid synchronization. The effects of frequency offset on stability have been evaluated using computer simulation. The simulation results have shown that the degradation of E/sub b//N/sub o/ at a BER of 10/sup -4/ is 1.4 dB, when the carrier frequency offset of an undesired signal is /spl plusmn/1 ppm and the desired-undesired signal power ratio is -30 dB. In the implemented AS-CDMA reverse link modem, the measured degradation of E/sub b//N/sub 0/ has been found to be 3.0 dB at a BER of 10/sup -4/.

Design and implementation of intracell reverse link using approximately synchronized CDMA

In this paper, Battery inspection system (BIS), for a high-speed data transmission in the internal energy management system (EMS) is proposed to reliably maintain charging and discharging batteries. For checking the state of charge (SOC) graph for 12 channels' voltage and temperature, the proposed system was designed to support a controller area network (CAN) interface operation with the speed of 500 kbps, 12-bits successive approximate register (SAR) typed analogue to digital converter (ADC) and a digital signal processing (DSP) processor with the operation speed of 300 MHz. It was conformed that the SOC results were stored in the DSP processor. This BIS system in EMS can be improved with real-time monitoring for the battery information in charging and discharging operation. It is expected to be effective in energy utilisation through BIS.

Implementation of battery inspection system for building energy management system

In this paper, it is reported that film-bulk-acoustic resonator with high c-axis oriented AIN film on using metal-organic-chemical-vapor deposition was fabricated. The resonant frequency and anti-resonant frequency of the fabricated resonator were observed with 3.189[GHz] and 3.224[GHz], respectively. The quality factor and the effective electromechanical coupling coefficient() were measured with 24.7 and 2.65[%], respectively. The conditions of AIN deposition were substrate temperature of , pressure of 20Torr, and V-III ratio of 25000. A high c-axis oriented AIN film with resistivity of Mo bottom electrode and of AIN(0002) full-width at half-maximum(FWHM) on was grown successfully. The FWHM value of deposited AIN film is useful for the RF band pass filter specification for GHz-band wireless local area network.

Jae-Sang Cha

Papers

Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor

Novel FFT LSI for Orthogonal Frequency Division Multiplexing Using Current Mode Circuit

Design and implementation of intracell reverse link using approximately synchronized CDMA

Implementation of battery inspection system for building energy management system

Fabrication of GHz-Band FBAR with AIN Film on Mo/SiO 2 /Si(100) Using MOCVD