This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%.

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

Cet article a pour but ďetudier les techniques de modulation multiporteuses dans le contexte des futurs reseaux sans fil a large bande Les differents systemes combinant des techniques a porteuses multiples et des techniques ďacces multiple par repartition en code (AMRC), notamment ľAMRC multiporteuse ou MC-CDMA, ľAMRC multiporteuses a sequence directe ou MC-DS-CDMA et ľAMRC multipilote ou MT-CDMA, sont tout ďabord presentes Puis, les systemes MC-CDMA sont etudies pour la liaison descendante de reseaux cellu-laires e haut debit Les performances de differentes techniques de detection mono-utilisateurs sont estimees analytiquement puis par simulation pour un canal de Rayleigh Les resultats de simulation comparant les performances de techniques de detection mono et multi-utilisateurs pour des canaux de type “Bad Urban” (BU), “Hilly Terrain” (HT) et “Vehicular” sont ensuite presentes Pour ces comparaisons, des codes convolutifs et des turbo-codes sont mis en oeuvre D’autre part, une nouvelle technique de detection appelee “Global Minimum Mean Square Error Algorithm ” (GMMSE) est comparee aux techniques de detection multi-utilisateurs a annulation parallele des brouillages Il est demontre que ľalgorithme GMMSE offre de bonnes performances en particulier lorsque le reseau n’est pas a pleine charge Ainsi, les systemes MC-CDMA apparaissent comme une technique ďacces multiple tres prometteuse et tres robuste pour la liaison descendante des futurs reseaux mobiles a large bande

Multicarrier CDMA techniques for future wideband wireless networks

Systems and methods are described for hybrid spread spectrum radio systems. A method includes modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control an amplification circuit that provides a gain to the signal. Another method includes: modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control a fast hopping frequency synthesizer; and fast frequency hopping the signal with the fast hopping frequency synthesizer, wherein multiple frequency hops occur within a single data-bit time.

Hybrid spread spectrum radio system

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radix rk single-path delay commutator/single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radix r, r 2, r 3, and r 4 decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms of r and the number of points of the FFT N. Expressions are given where it is not necessary that N is a power of rk. The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2, 22, 23, and 24, and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radix rk pipeline architectures when k > 4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value of N.

Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

Fast OFDM: A proposal for doubling the data rate of OFDM schemes

Memory references in digital signal processors (DSP) are expensive due to their long latencies and high power consumption. Implementing fast Fourier transform (FFT) algorithms on DSP involves many memory references to access butterfly inputs and twiddle factors. Conventional FFT implementations require redundant memory references to load identical twiddle factors for butterflies from different stages in the FFT diagrams. In this paper, we present novel memory reference reduction methods to minimize memory references due to twiddle factors for implementing various different FFT algorithms on DSP. The proposed methods first group the butterflies with identical twiddle factors from different stages in the FFT diagrams and compute them before computing other butterflies with different twiddle factors, and then reduce the number of twiddle factor lookups by taking advantage of the properties of twiddle factors. Consequently, each twiddle factor is loaded only once and the number of memory references due to twiddle factors can be minimized. We have applied the proposed methods to implement radix-2 DIF FFT algorithm on TI TMS320C64x DSP. Experimental results show the proposed methods can achieve average of 76.4% reduction in the number of memory references, 53.5% saving of memory spaces due to twiddle factors, and average of 36.5% reduction in the number of clock cycles to compute radix-2 DIF FFT on DSP comparing to the conventional implementation. Similar performance gain is reported for implementing radix-2 DIT FFT algorithms using the new methods

Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors

This paper proposes the modified radix-2/sup 4/ and the radix-4/sup 2/ FFT algorithms and efficient pipeline FFT architectures based on those algorithms for OFDM systems. The proposed pipeline FFT architectures have the same number of multipliers as that of the conventional R2/sup 2/SDF and R4SDC. However, the multiplication complexity and the ROMs for storing twiddle factors could be reduced by more than 30% and 50% respectively by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 /spl mu/m CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area and power efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

http://ieeexplore.ieee.org/iel5/10549/33371/01579923.pdf

Area and power efficient pipeline FFT algorithm

In this paper, a new Radix-N pipeline fast Fourier transform (FFT) processor for the implementation of IEEE 802.11a baseband orthogonal frequency division multiplexing (OFDM) modem for wireless local area network (WLAN) is proposed. The newly proposed scheme has a simple control structure and multiplication block is designed based on canonic signed digit (CSD) with N/4 twiddle factors, which enables both hardware complexity and power consumption to be reduced as about less 33% and 66% respectively than the conventional Radix-4 pipeline and Radix-2 pipeline structures. In order to verify the real time operation, the IEEE802.11a baseband OFDM test-bed with the newly proposed Radix-N pipeline FFT processor is implemented using field programmable gate array (FPGA) devices.

https://iopscience.iop.org/article/10.1143/JJAP.42.2176/pdf

Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor

It is necessary to devise the method for increasing the bandwidth efficiency in order to provide the high speed mobile multimedia communication services with CDMA under the limited radio bandwidth resources. In this paper the structure for transmitting the high-speed data at the half bandwidth of the required bandwidth using the symmetry property of the IFFT output of the binary input MC-CDMA, which enables the time scaling method utilized, is proposed. The processing gain is increased 4 times than the DS-CDMA and its performance is evaluated to be compared with DS-CDMA with RAKE receivers under the Rayleigh fading channel and same bandwidth per one channel.

The bandwidth efficiency increasing method of multi-carrier CDMA and its performance evaluation in comparison with DS-CDMA with RAKE receivers

This paper proposes a new efficient FFT architecture with structured pipeline for OFDM systems, based on radix-2/sup 4/ algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2/sup 2/ algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multiplier can enhance the area/power efficiency of the design. From synthesis simulations of a standard 0.35/spl mu/m CMOS process, it achieved above 60% area reduction when compared with the conventional programmable multiplier.

Myoung-Seob Lim

Papers

Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors

Area and power efficient pipeline FFT algorithm

Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor

The bandwidth efficiency increasing method of multi-carrier CDMA and its performance evaluation in comparison with DS-CDMA with RAKE receivers

Fast Fourier transform processor based on low-power and area-efficient algorithm