IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Background Human cognitive functioning can be assessed using different methods of testing. Age, level of education, and gender may influence the results of cognitive tests. Material and methods The well-known Trail Making Test (TMT), which is often used to measure the frontal lobe function, and the experimental test of Interval Timing (IT) were compared. The methods used in IT included reproduction of auditory and visual stimuli, with the subsequent production of the time intervals of 1-, 2-, 5-, and 7-seconds durations with no pattern. Subjects included 64 healthy adult volunteers aged 18-63 (33 women, 31 men). Comparisons were made based on age, education, and gender. Results TMT was performed quickly and was influenced by age, education, and gender. All reproduced visual and produced intervals were shortened and the reproduction of auditory stimuli was more complex. Age, education, and gender have more pronounced impact on the cognitive test than on the interval timing test. The reproduction of the short auditory stimuli was more accurate in comparison to other modalities used in the IT test. Conclusions The interval timing, when compared to the TMT, offers an interesting possibility of testing. Further studies are necessary to confirm the initial observation.

Evaluation of the Trail Making Test and interval timing as measures of cognition in healthy adults: comparisons by age, education, and gender.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

EDT Bandwidth Management in SoC Designs

In this paper, we propose a method of minimizing test time in SoCs (System-on-chip), for a given power budget, by varying the test clock frequency for each test session. Since frequency is proportional to the test time and the power dissipated, by controlling the test clock frequency, the power dissipated and the test time per session can be adjusted so as to yield an optimal solution to the test scheduling problem. To achieve this, we modify the existing ILP (Integer-Linear Program) model for optimal test scheduling to include a variable frequency parameter which, in turn, controls the test time and power. For the optimization, we have used an open-source ILP solver. We also prove that the lower bound on the total test time of an SoC, is obtained by executing individual cores (tests) per session at their maximum frequency of operation, such that their test power is same as the power budget. Results show an improvement of 27% over existing solution for the benchmark SoC, ASIC Z.

/pdf/optimal-power-constrained-soc-test-schedules-with-28a65ztnui.pdf

Optimal power-constrained SoC test schedules with customizable clock rates

High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.

Achieving extreme scan compression for SoC Designs

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

Dynamic channel allocation for higher EDT compression in SoC designs

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

EDT bandwidth management - Practical scenarios for large SoC designs

This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.

Jakub Janicki

Papers

EDT Bandwidth Management in SoC Designs

Dynamic channel allocation for higher EDT compression in SoC designs

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

EDT bandwidth management - Practical scenarios for large SoC designs

Bandwidth-aware test compression logic for SoC designs